Parallella RISC-V Prebuilt Images
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Updated
Aug 18, 2016
Parallella RISC-V Prebuilt Images
A simple baremetal program template for RISC-V inspired from riscv benchmark tests
RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
BOOM's Simulation Accelerator.
A fault-injection framework using Chisel and FIRRTL
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
Network components (NIC, Switch) for FireBox
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
SonicBOOM: The Berkeley Out-of-Order Machine
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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