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netlist

Here are 37 public repositories matching this topic...

SubZer0811 / BE2SIM

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

postfix boolean-expression netlist irsim circuit-netlist-description sim-file

Updated Sep 28, 2020
Python

DevinduDh / LTspice-projects

LTSpice projects

delay schematic sizing netlist propagation-delay capacitance rise-time fall-time ltspice slew-rate slew gate-delay rise-delay fall-delay inverter-sizing step-parameter

Updated Feb 15, 2024
AGS Script

JensRestemeier / EdifTests

A few experiments using the SpyDrNet netlist library.

netlist edif spydrnet

Updated Mar 31, 2021
Python

jvestman / skimibowi

SKiDL Microcontroller Board Wizard

pyqt5 wizard kicad netlist microcontroller-boards netlists circuits-and-electronics

Updated Sep 23, 2023
Python

pablov55 / Beginner-s-Guide-to-KiCad

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

Updated Apr 8, 2024
HTML

rohankalbag / logic-simulator

Course Assignment - Foundations of VLSI CAD - Autumn Semester 2022 - Indian Institute of Technology Bombay

python netlist combinational-circuit logic-simulator vlsi-cad

Updated Dec 10, 2022
Jupyter Notebook

arhamhashmi01 / openlane-verification

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

opensource verification synthesis gds cts netlist placement klayout floorplan openlane openlane-flow openlane-github- netlist-simulation-

Updated Mar 8, 2024
Verilog

CIDARLAB / miniFluigi

A more modular Fluigi Codebase

routing-engine microfluidics netlist fluigi placement-engine

Updated Feb 20, 2020
Java

circuitgraph / circuitsim

Perform gate-level simulations from python

python simulation eda netlist boolean-circuits

Updated Mar 20, 2023
Python

kitanokitsune / S-expression-library-for-Python

S-expression data structure parser/manipulator intended for parsing and manipulating lisp program, lisp data, netlists like EDIF and KiCAD, etc.

python library lisp cad s-expressions netlist edif

Updated Feb 15, 2023
Python

LCSR-lab / MODNET

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

python vhdl pip verilog fault-injection netlist modnet synplify-pro

Updated Jun 27, 2021
Python

LCSR-lab / NetFi3

NetFI-3: Netlist Fault Injection system - Version 3

computer-science engineering thesis vhdl computer-engineering verilog vivado fault-injection netlist nexys4

Updated Jun 29, 2020
TeX

jamestiotio / compstruct

SUTD 2020 50.002 Computation Structures Code Dump

cpu fpga hardware beta os operating-system turing-machine lucid computer-architecture risc turing-machine-simulator netlist instruction-set-architecture instruction-set digital-systems hardware-description-language computation-structures netlist-simulator central-processing-unit

Updated Apr 7, 2022
C

chmod775 / trace

Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.

javascript automation hardware electronics pcb eda schematics kicad hdl netlist

Updated Dec 6, 2021
JavaScript

muhammadtalhasami / openlane

This is my openlane repository in which we perform synthesis of our design/module.

synthesis netlist klayout openlane openlane-flow muhammadtalhasami-github- openlanegithub- openlane-github- muhammad-talha-github- desgin-synthesis- netlist-simulation- floorplan- placement- rounting- cts-

Updated Mar 17, 2024
Tcl

shishir-dey / vhdl-samples

Contains VHDL netlists of basic digital circuits.

vhdl hardware-designs testbench netlist

Updated Mar 9, 2019
VHDL

najaeda / naja-verilog

A standalone structural (gate-level) verilog parser

parser cpp eda verilog netlist semiconductor netlist-parser electronic-design-automation

Updated Apr 2, 2024
C++

amfl / short-circuit

tile-based digital logic sandbox

terminal-based netlist

Updated Sep 10, 2021
Python

emsec / hal-benchmarks

Benchmark suite for HAL

hardware vhdl reverse-engineering verilog netlist

Updated Nov 9, 2020
VHDL

FPGAsm / FPGAsm

A low-level hierarchical netlist assembler for FPGAs

fpga netlist netlists hdls

Updated Jul 26, 2021
C++

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