Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the fun…

🔁 Form multiplier & replicator for Nette Framework

16-bit Adder Multiplier hardware on Digilent Basys 3

An unsupervised transfer learning approach for rare disease transcriptomics

The Verilog source code for DRUM approximate multiplier.

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

A VHDL code generator for wallace tree multiplier

Posit Arithmetic Cores generated with FloPoCo

VHDL implementation of the Booth's multiplication algorithm

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

This project was performed on the completion of our B. Tech 4th Semester Summer Training cum Academic Internship Programme on "RISC-V based 32-bit Digital Processor Design using SPICE" under E&ICT Academy IIT Guwahati and Assam Science & Technology University, Guwahati under TEQIP III in association with VLSI Expert

Booth encoded Wallace tree multiplier

32-bit Wallace and Dadda Tree Multiplier

This repository contains approximate 8-bit multiplier Verilog code.

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

COA OEE (ASM)

Source code for pure combinational 16 bit integer multiplier hardware

A Parallel Multiplier Using SystemVerilog HDL

Bingo game with score

Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier