Graphical-Micro-Architecture-Simulator
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Updated
Apr 12, 2024 - JavaScript
Graphical-Micro-Architecture-Simulator
Parser for legv8sim from Nom that converts to an intermediate representation to interpret a legv8 program
A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog
ARM Assembly Gradient Descent Program
A LEGv8 Language Server that implements the Microsof Language Server Protocol.
Insertion sort implemented in LEGv8 assembly as required by Computer Science 321 @ Iowa State University, Fall 2021.
A disassembler for LEGv8 machine code as required by Computer Science 321 @ Iowa State University, Fall 2021.
Bitonic Sort in a simplified ARMv8 Assembly language
LEGv8 CPU implementation and some tools like a LEGv8 assembler
Verilog Implementation of an ARM LEGv8 CPU
Verilog Implementation of an ARM LEGv8 CPU
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