The definition document for the AVRA computer architecture
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Updated
Feb 4, 2021
The definition document for the AVRA computer architecture
Testing out optimal magic numbers for the old fast inverse square root function.
Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.
An assignment using the ARMv6-M ISA to explore the concepts of memory size.
An assignment introducing the concept of an Instruction Set Architecture (ISA) via the CARDIAC paper computer.
Processor Architecture Simulator supporting basic instructions from IS.
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.
Assembler implementation or the Hack computer from the Nand To Tetris course.
An 8-bit ISA and CPU implementation in Minecraft.
A virtual computer build from scratch that can play Tetris: from binary to OOP
7 Stage APEX Pipeline based on instructions flow in a Computer Architecture
An assignment introducing the ARMv6-M architecture and debugging with the Raspberry Pi Pico.
A assembler and simulator for a custom RISC ISA
18-bit processor implementation using Logisim
NASM x86 compatable assembly language educational materials
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
synacor challenge
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