The definition document for the AVRA computer architecture
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Updated
Feb 4, 2021
The definition document for the AVRA computer architecture
RISC-V 64-bit with 32-bit floating point extension support.
Testing out optimal magic numbers for the old fast inverse square root function.
Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.
A fantasy computer with 16 instructions.
A collection of assembly files written for class assignments
An assignment using the ARMv6-M ISA to explore the concepts of memory size.
An assignment introducing the concept of an Instruction Set Architecture (ISA) via the CARDIAC paper computer.
My attempt at a CPU simulator
A small toy VM and assembler written in python as a learning exercise. Has 3 registers, with storage, maths and printing.
Assembler implementation or the Hack computer from the Nand To Tetris course.
An 8-bit ISA and CPU implementation in Minecraft.
RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.
A virtual computer build from scratch that can play Tetris: from binary to OOP
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
The JadeLang Stack-Based Virtual Machine
Processor Architecture Simulator supporting basic instructions from IS.
This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.
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