A High-performance Timing Analysis Tool for VLSI Systems
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Updated
May 26, 2023 - Verilog
A High-performance Timing Analysis Tool for VLSI Systems
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
A Standalone Structural Verilog Parser
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
VLSI EDA Global Router
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
EDA Analytics Central
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
Characterizing and Optimizing EDA Flows for the Cloud (DATE'2021 and TCAD)
Provides a packaged collection of open source EDA tools
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!
Find a part on Digi-Key and import parameters into local database
Awesome machine learning for logic synthesis
Color Balancing for Double Patterning, problem E of CAD contest 2015
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