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Teaching Materials for Dr. Waleed A. Yousef

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

SystemVerilog examples for a digital design course

A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

The project uses a Xilinx Artix-7 FPGA on a Digilent Basys 3 board to design a clock whose seconds, minutes, & hours are displayed on a Quad 7-segment display & can also be displayed on a vga display. Picoblaze processor is used to control the Analog & Digital displays of the clock.

Python script for generating lookup tables for the gm/ID design methodology and much more ...

An introduction to integrated circuit design with Verilog and the Papilio Pro development board.

This repository contains projects done by undergraduate students of IIT Jodhpur in the areas of Indigenous Digital Design and Electronic Design Automation (IDDEDA).

32 bit pipelined binary floating point adder using IEEE-754 Single Precision Format in Verilog

VHDL code examples for a digital design course

Generator for wokwi schematics that implement lookup tables in conjunctive normal form (CNF), i.e. with AND and OR gates

An open source, parameterized SystemVerilog digital hardware IP library

Materials for the Computer Science course, Digital Design (Logic Circuits)

This project is to implement a combination lock on the FPGA board using VHDL language and finite state machine. There are some possible solutions are provided to address the problems including debounce, random number generation and combination check.

Design and implement the following components of the SPI modules using Verilog such that they match the requirements of the development testbench and match the SPI specifications: Master-Slave Self-Checking Testbenches for the Master and Slave

Term project for CS223 Digital - Design course.

Design and implementation an arithmetic unit that is capable of adding, subtracting, and multiplying two signed magnitude numbers, and displays the result of the operation performed along with some additional flags regarding the operation and the result using Logisim.

EE4415 Project : AES Verilog