digital-design
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Cuarto laboratorio del curso de Taller de Diseño Digital. La idea es generar un código compilable para una FPGA con la que se pueda simular el funcionamiento de máquina de café utilizando el lenguaje de programación SystemVerilog.
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May 5, 2022 - SystemVerilog
Moore.io Demo Project
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Mar 29, 2023 - SystemVerilog
A RISC custom-ISA, 16-Bit Processor
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Oct 2, 2023 - C
Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay
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Apr 5, 2024 - VHDL
AdobeAllInOne is a comprehensive suite of creative software tools developed by Adobe. It includes a range of applications for design, photography, video editing, and more, making it the ultimate solution for all your creative needs.
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Apr 9, 2024 - AutoIt
🖋 Typeset Quartus II schematics using TikZ (LaTeX)
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Sep 6, 2023 - Python
This repository contains project work for the Digital Systems course. The projects cover fundamental topics of digital design including Boolean algebra, combinational logic, sequential logic, and state machine design
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Aug 2, 2023
SUSTech CS207 Digital Design 2018Fall Materials.
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Jun 26, 2022 - Verilog
This is Official CircuitVerse Online Documentation
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Jun 30, 2020
Repository for lab component of the course CS F215: Digital Design at BITS Pilani, Pilani campus (Fall '21)
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Dec 5, 2021
Educational repo for storing my practice sessions with digital systems as well as solutions to online courses or university courses I take. These implementations are done in VHDL or Verilog.
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Sep 18, 2021 - VHDL
booth's multiplier defined by datapath and control path , where controller generates different control signals which are used by different modules to generate product
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Aug 27, 2021 - Verilog
A DDS peripheral for an Altera Cyclone V computer to produce sine waves and musical notes
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May 2, 2023 - VHDL
Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method
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Feb 14, 2023 - VHDL
Sample Verilog codes for digital circuits
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Oct 22, 2023 - Verilog
An NPU designed using an LLM with a single prompt
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Sep 11, 2023 - Verilog
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