Repository regarding the Practical Works of the Computer Organization discipline
-
Updated
Dec 30, 2020 - Verilog
Repository regarding the Practical Works of the Computer Organization discipline
A Datapath design which able to execute store operation as memory instruction, substraction and or operations as arithmetic instruction by Logisim. Additional explanations in readme.
Calculadora eletrônica feita no simulador Circuit Verse, realiza soma de 2 números de 0 a 99, conversão bin2dec e dec2bin.
Implements a datapath which is capable of executing a subset of the Motorola HC08 instruction set on a Field Programmable Gate Array (FPGA).
datapath risc-v with pipeline
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
MIPS Multicycle CPU design in Verilog
This repository contains Risc V 32 bit single cycle data path simulated on Logism upon loading instructions.
📈 House Price Prediction in Verilog, Computer Architecture course, University of Tehran
In a Single Cycle Datapath, each of the Datapath's components carries out an instruction in one cycle. Therefore, no Datapath component may be utilized more than once each cycle.
University project about the game rock-paper-scissors
designing RISC-V architecture using Verilog HDL in XILINX VIVADO PC SUITE
🕹️ Mastermind game written in VHDL
Add a description, image, and links to the datapath topic page so that developers can more easily learn about it.
To associate your repository with the datapath topic, visit your repo's landing page and select "manage topics."