axi4
Here are 48 public repositories matching this topic...
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
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Jun 6, 2020 - C++
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
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Jul 25, 2020 - Tcl
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
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Aug 8, 2020 - Tcl
Minimal DVI / HDMI Framebuffer
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Aug 9, 2020 - Verilog
A demonstrator of Hermes network-on-chip communicating with the ARM processor
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Aug 10, 2020 - Tcl
AXI4 and AXI4-Lite interface definitions
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Sep 20, 2020 - SystemVerilog
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
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Oct 13, 2020 - C++
HLS for Networks-on-Chip
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Feb 18, 2021 - C++
A collection of formal properties for hardware buses, and cores using them.
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Feb 22, 2021 - Verilog
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