The TART project has been developed by:
- Tim Molteno: Overall system design, software, tim@elec.ac.nz
- Phill Brown: Hardware design
- Charles Shaw: TART 1 and early phase project
- Max Scheel: TART 2 and imaging algorithms
- Mike Field (HamsterNZ): Memory Controller for SDRAM.
- Pat Suggate: Real-time FPGA correlator
- Tim Miller: Web-App interface
- Simon Harvey: Web-App interface
- Mytchel Hammond: TART3 FPGA and Xilinx Zync kernel