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Is it possible to generate OpenCL kernels with TACO? #543

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rdguerrerom opened this issue Jan 24, 2023 · 6 comments
Open

Is it possible to generate OpenCL kernels with TACO? #543

rdguerrerom opened this issue Jan 24, 2023 · 6 comments

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@rdguerrerom
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Could TACO be used to generate OpenCL kernels? If not, what should be modified to allow OpenCL kernel generation?

@rohany
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rohany commented Jan 24, 2023

In theory TACO could be used to generate OpenCL kernels, but cannot currently. If you were interested in such a thing, looking at codegen_cuda.cpp would be the place to start. It lowers a loop-based intermediate representation into CUDA code. If your goal is to target AMD GPUs, targeting HIP would be the easiest thing instead, as you could just replace all of the CUDA calls with the corresponding HIP calls.

@rdguerrerom
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Thanks a lot for answering,

The goal that I have in mind is to use FPGAs for which I think that the code generation shall target OpenCL-C.

@rohany
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rohany commented Jan 24, 2023

Targeting different kinds of hardware will likely be more work than just adjusting the code generator. @weiya711 has been working on mapping TACO down to CGRA's and other accelerators and can comment more.

@rdguerrerom
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Yes, I agree with you @rohany. However, initially being able to generate kernels in OpenCL-C will suffice. Will a sensible modification of codegen_cuda.cpp be enough to accomplish this task?

@rohany
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rohany commented Jan 24, 2023

I've never written OpenCL targeting FPGA's before, so I cannot say for certain. The farther away this programming model moves from the threaded style of GPU programming the harder it will be to accomplish your task with just a change to the code generator. As Olivia has done in her work, for different programming models, and entirely different compilation workflow is needed to effectively target them.

@rdguerrerom
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Please allow me to insist. It will be sufficient to modify codegen_cuda.cpp in order to generate OpenCL-C code, The OpenCL-C standard is fully supported by OneAPI, which allows running a program on an FPGA in emulation mode for debugging and also allows for hardware compilation.

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