Challenges to RISC0 on bare metal and embedded systems #700
l-monninger
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I'm interested in experimenting with RISC0. Long term, I'm particularly curious about embedded applications, i.e., running RISC0 on Xtensa, Arm Cortex-M, etc. What, if any, parts of the existing source should be portable? Besides general memory constraints, what else might pose significant obstacles to using RISC0 in an embedded context?
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