{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":83772175,"defaultBranch":"main","name":"cpuinfo","ownerLogin":"pytorch","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2017-03-03T07:46:54.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/21003710?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1670354301.1507819","currentOid":""},"activityList":{"items":[{"before":"5de5c70fedc26e4477d14fdaad0e4eb5f354400b","after":"3c8b1533ac03dd6531ab6e7b9245d488f13a82a5","ref":"refs/heads/main","pushedAt":"2024-04-17T15:29:37.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"add detection for intel new isa: avx_ne_convert, avx_vnni_int8, avx_vnni_int16 (#232)\n\nTest Plan:\r\n```\r\nbash scripts/local-build.sh\r\n\r\nISAS=()\r\nOPTIONS=()\r\nPLATFORMS=()\r\n\r\nOPTIONS+=(-quark); PLATFORMS+=(\"Quark\")\r\nOPTIONS+=(-p4); PLATFORMS+=(\"Pentium4\")\r\nOPTIONS+=(-p4p); PLATFORMS+=(\"Pentium4 Prescott\")\r\nOPTIONS+=(-mrm); PLATFORMS+=(\"Merom\")\r\nOPTIONS+=(-pnr); PLATFORMS+=(\"Penryn\")\r\nOPTIONS+=(-nhm); PLATFORMS+=(\"Nehalem\")\r\nOPTIONS+=(-wsm); PLATFORMS+=(\"Westmere\")\r\nOPTIONS+=(-snb); PLATFORMS+=(\"Sandy Bridge\")\r\nOPTIONS+=(-ivb); PLATFORMS+=(\"Ivy Bridge\")\r\nOPTIONS+=(-hsw); PLATFORMS+=(\"Haswell\")\r\nOPTIONS+=(-bdw); PLATFORMS+=(\"Broadwell\")\r\nOPTIONS+=(-slt); PLATFORMS+=(\"Saltwell\")\r\nOPTIONS+=(-slm); PLATFORMS+=(\"Silvermont\")\r\nOPTIONS+=(-glm); PLATFORMS+=(\"Goldmont\")\r\nOPTIONS+=(-glp); PLATFORMS+=(\"Goldmont Plus\")\r\nOPTIONS+=(-tnt); PLATFORMS+=(\"Tremont\")\r\nOPTIONS+=(-snr); PLATFORMS+=(\"Snow Ridge\")\r\nOPTIONS+=(-skl); PLATFORMS+=(\"Skylake\")\r\nOPTIONS+=(-cnl); PLATFORMS+=(\"Cannon Lake\")\r\nOPTIONS+=(-icl); PLATFORMS+=(\"Ice Lake\")\r\nOPTIONS+=(-skx); PLATFORMS+=(\"Skylake server\")\r\nOPTIONS+=(-clx); PLATFORMS+=(\"Cascade Lake\")\r\nOPTIONS+=(-cpx); PLATFORMS+=(\"Cooper Lake\")\r\nOPTIONS+=(-icx); PLATFORMS+=(\"Ice Lake server\")\r\nOPTIONS+=(-knl); PLATFORMS+=(\"Knights landing\")\r\nOPTIONS+=(-knm); PLATFORMS+=(\"Knights mill\")\r\nOPTIONS+=(-tgl); PLATFORMS+=(\"Tiger Lake\")\r\nOPTIONS+=(-adl); PLATFORMS+=(\"Alder Lake\")\r\nOPTIONS+=(-mtl); PLATFORMS+=(\"Meteor Lake\")\r\nOPTIONS+=(-rpl); PLATFORMS+=(\"Raptor Lake\")\r\nOPTIONS+=(-spr); PLATFORMS+=(\"Sapphire Rapids\")\r\nOPTIONS+=(-gnr); PLATFORMS+=(\"Granite Rapids\")\r\nOPTIONS+=(-gnr256); PLATFORMS+=(\"Granite Rapids (AVX10.1 / 256VL)\")\r\nOPTIONS+=(-srf); PLATFORMS+=(\"Sierra Forest\")\r\nOPTIONS+=(-arl); PLATFORMS+=(\"Arrow Lake\")\r\nOPTIONS+=(-lnl); PLATFORMS+=(\"Lunar Lake\")\r\nOPTIONS+=(-future); PLATFORMS+=(\"Future chip\")\r\n\r\nISAS+=(\"AVX_VNNI_INT8\")\r\nISAS+=(\"AVX_VNNI_INT16\")\r\nISAS+=(\"AVX_NE_CONVERT\")\r\n\r\nSDE_BIN=\"/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde\"\r\n\r\nfor I in \"${!PLATFORMS[@]}\"; do\r\n  echo \"${PLATFORMS[\"${I}\"]}\"\r\n    for J in \"${!ISAS[@]}\"; do\r\n      \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep ${ISAS[$J]}\r\n    done\r\ndone\r\n```\r\n\r\nResults:\r\n```\r\nQuark\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nPentium4\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nPentium4 Prescott\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nMerom\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nPenryn\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nNehalem\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nWestmere\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSandy Bridge\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nIvy Bridge\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nHaswell\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nBroadwell\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSaltwell\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSilvermont\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nGoldmont\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nGoldmont Plus\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nTremont\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSnow Ridge\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSkylake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nCannon Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nIce Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSkylake server\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nCascade Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nCooper Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nIce Lake server\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nKnights landing\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nKnights mill\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nTiger Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nAlder Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nMeteor Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nRaptor Lake\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSapphire Rapids\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nGranite Rapids\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nGranite Rapids (AVX10.1 / 256VL)\r\n        AVX_VNNI_INT8: no\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: no\r\nSierra Forest\r\n        AVX_VNNI_INT8: yes\r\n        AVX_VNNI_INT16: no\r\n        AVX_NE_CONVERT: yes\r\nArrow Lake\r\n        AVX_VNNI_INT8: yes\r\n        AVX_VNNI_INT16: yes\r\n        AVX_NE_CONVERT: yes\r\nLunar Lake\r\n        AVX_VNNI_INT8: yes\r\n        AVX_VNNI_INT16: yes\r\n        AVX_NE_CONVERT: yes\r\nFuture chip\r\n        AVX_VNNI_INT8: yes\r\n        AVX_VNNI_INT16: yes\r\n        AVX_NE_CONVERT: yes\r\n```","shortMessageHtmlLink":"add detection for intel new isa: avx_ne_convert, avx_vnni_int8, avx_v…"}},{"before":"f42f5eaf0bbeabd3a1153651cd2a5989faac4f58","after":"5de5c70fedc26e4477d14fdaad0e4eb5f354400b","ref":"refs/heads/main","pushedAt":"2024-04-17T14:16:56.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Fixing Ampere Altra Processor detection (#237)\n\n**Summary:**\r\n\r\nResolves #236\r\n\r\nAlso related to [PR 220](https://github.com/pytorch/cpuinfo/pull/220) change.\r\n\r\n```\r\n\"Unknown chip model name 'Ampere(R) Altra(R) Processor'.\r\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!\"\r\n```\r\n\r\n---\r\n\r\n**Previous error details:**\r\n\r\nThe error's reason was:\r\n\r\n`woa_chip_name` (`windows-arm-init.h`)  enum had only 4 elements (stored in `woa_chip_name_last`)\r\n\r\n```c\r\nenum woa_chip_name {\r\n\twoa_chip_name_microsoft_sq_1 = 0,\r\n\twoa_chip_name_microsoft_sq_2 = 1,\r\n\twoa_chip_name_microsoft_sq_3 = 2,\r\n\twoa_chip_name_ampere_altra = 3,\r\n\twoa_chip_name_unknown = 4,\r\n\twoa_chip_name_last = woa_chip_name_unknown\r\n};\r\n```\r\n\r\nHowever, `woa_chips[]`  (`init.c`) has a duplicated value for `woa_chip_name_microsoft_sq_3` due to different strings for same target after the [PR 220](https://github.com/pytorch/cpuinfo/pull/220)\r\n\r\n> Strings are `Snapdragon (TM) 8cx Gen 3` and `Snapdragon Compute Platform`\r\n\r\nAnd this was causing following `for loop` (`init.c`) is not checking for all elements in `woa_chips[]`.\r\n\r\n```c\r\nfor (uint32_t i = 0; i < (uint32_t)woa_chip_name_last; i++) {\r\n\tsize_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX);\r\n\tint compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length);\r\n\tif (compare_result == 0) {\r\n\t\tchip_info = woa_chips + i;\r\n\t\tbreak;\r\n\t}\r\n}\r\n```\r\n\r\n---\r\n\r\n**Fix Details:**\r\n\r\nWe added `woa_chip_name_microsoft_sq_3_devkit` to maintain **one to one** relationship between `woa_chip_name` (`windows-arm-init.h`) and `woa_chips[]` (`init.c`).\r\n\r\nAlso, we especially specified indexes with `enums` to prevent future duplications and increase readability of the code and relationship.","shortMessageHtmlLink":"Fixing Ampere Altra Processor detection (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2238518998\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/237\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/237/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/237\">#237</a>)"}},{"before":"6543fec09b2f04ac4a666882998b534afc9c1349","after":"f42f5eaf0bbeabd3a1153651cd2a5989faac4f58","ref":"refs/heads/main","pushedAt":"2024-03-28T06:03:24.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Add detection for Intel Advanced Matrix Extensions (AMX) instructions (#231)\n\nTested using intel SDE: https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html\r\n\r\nTest scripts:\r\n```\r\nbash scripts/local-build.sh\r\n\r\nISAS=()\r\nOPTIONS=()\r\nPLATFORMS=()\r\n\r\nOPTIONS+=(-quark); PLATFORMS+=(\"Quark\")\r\nOPTIONS+=(-p4); PLATFORMS+=(\"Pentium4\")\r\nOPTIONS+=(-p4p); PLATFORMS+=(\"Pentium4 Prescott\")\r\nOPTIONS+=(-mrm); PLATFORMS+=(\"Merom\")\r\nOPTIONS+=(-pnr); PLATFORMS+=(\"Penryn\")\r\nOPTIONS+=(-nhm); PLATFORMS+=(\"Nehalem\")\r\nOPTIONS+=(-wsm); PLATFORMS+=(\"Westmere\")\r\nOPTIONS+=(-snb); PLATFORMS+=(\"Sandy Bridge\")\r\nOPTIONS+=(-ivb); PLATFORMS+=(\"Ivy Bridge\")\r\nOPTIONS+=(-hsw); PLATFORMS+=(\"Haswell\")\r\nOPTIONS+=(-bdw); PLATFORMS+=(\"Broadwell\")\r\nOPTIONS+=(-slt); PLATFORMS+=(\"Saltwell\")\r\nOPTIONS+=(-slm); PLATFORMS+=(\"Silvermont\")\r\nOPTIONS+=(-glm); PLATFORMS+=(\"Goldmont\")\r\nOPTIONS+=(-glp); PLATFORMS+=(\"Goldmont Plus\")\r\nOPTIONS+=(-tnt); PLATFORMS+=(\"Tremont\")\r\nOPTIONS+=(-snr); PLATFORMS+=(\"Snow Ridge\")\r\nOPTIONS+=(-skl); PLATFORMS+=(\"Skylake\")\r\nOPTIONS+=(-cnl); PLATFORMS+=(\"Cannon Lake\")\r\nOPTIONS+=(-icl); PLATFORMS+=(\"Ice Lake\")\r\nOPTIONS+=(-skx); PLATFORMS+=(\"Skylake server\")\r\nOPTIONS+=(-clx); PLATFORMS+=(\"Cascade Lake\")\r\nOPTIONS+=(-cpx); PLATFORMS+=(\"Cooper Lake\")\r\nOPTIONS+=(-icx); PLATFORMS+=(\"Ice Lake server\")\r\nOPTIONS+=(-knl); PLATFORMS+=(\"Knights landing\")\r\nOPTIONS+=(-knm); PLATFORMS+=(\"Knights mill\")\r\nOPTIONS+=(-tgl); PLATFORMS+=(\"Tiger Lake\")\r\nOPTIONS+=(-adl); PLATFORMS+=(\"Alder Lake\")\r\nOPTIONS+=(-mtl); PLATFORMS+=(\"Meteor Lake\")\r\nOPTIONS+=(-rpl); PLATFORMS+=(\"Raptor Lake\")\r\nOPTIONS+=(-spr); PLATFORMS+=(\"Sapphire Rapids\")\r\nOPTIONS+=(-gnr); PLATFORMS+=(\"Granite Rapids\")\r\nOPTIONS+=(-gnr256); PLATFORMS+=(\"Granite Rapids (AVX10.1 / 256VL)\")\r\nOPTIONS+=(-srf); PLATFORMS+=(\"Sierra Forest\")\r\nOPTIONS+=(-arl); PLATFORMS+=(\"Arrow Lake\")\r\nOPTIONS+=(-lnl); PLATFORMS+=(\"Lunar Lake\")\r\nOPTIONS+=(-future); PLATFORMS+=(\"Future chip\")\r\n\r\nISAS+=(\"AMXBF16\")\r\nISAS+=(\"AMXTILE\")\r\nISAS+=(\"AMXINT8\")\r\nISAS+=(\"AMXFP16\")\r\n\r\nSDE_BIN=\"/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde\"\r\n\r\nfor I in \"${!PLATFORMS[@]}\"; do\r\n  echo \"${PLATFORMS[\"${I}\"]}\"\r\n    for J in \"${!ISAS[@]}\"; do\r\n      \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep ${ISAS[$J]}\r\n    done\r\ndone\r\n```\r\n\r\n\r\nResults:\r\n```\r\nQuark\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file\r\nPentium4\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nSDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file\r\nPentium4 Prescott\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nMerom\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nPenryn\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nNehalem\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nWestmere\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSandy Bridge\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nIvy Bridge\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nHaswell\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nBroadwell\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSaltwell\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSilvermont\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nGoldmont\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nGoldmont Plus\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nTremont\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSnow Ridge\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSkylake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nCannon Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nIce Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSkylake server\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nCascade Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nCooper Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nIce Lake server\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nKnights landing\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nKnights mill\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nTiger Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nAlder Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nMeteor Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nRaptor Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nSapphire Rapids\r\n        AMXBF16: yes\r\n        AMXTILE: yes\r\n        AMXINT8: yes\r\n        AMXFP16: no\r\nGranite Rapids\r\n        AMXBF16: yes\r\n        AMXTILE: yes\r\n        AMXINT8: yes\r\n        AMXFP16: yes\r\nGranite Rapids (AVX10.1 / 256VL)\r\n        AMXBF16: yes\r\n        AMXTILE: yes\r\n        AMXINT8: yes\r\n        AMXFP16: yes\r\nSierra Forest\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nArrow Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nLunar Lake\r\n        AMXBF16: no\r\n        AMXTILE: no\r\n        AMXINT8: no\r\n        AMXFP16: no\r\nFuture chip\r\n        AMXBF16: yes\r\n        AMXTILE: yes\r\n        AMXINT8: yes\r\n        AMXFP16: yes\r\n```","shortMessageHtmlLink":"Add detection for Intel Advanced Matrix Extensions (AMX) instructions (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2205065369\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/231\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/231/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/231\">…</a>"}},{"before":"fb08ae018ef8d8f71e3a2960c0982f90b688fe06","after":"6543fec09b2f04ac4a666882998b534afc9c1349","ref":"refs/heads/main","pushedAt":"2024-03-17T00:45:02.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Include support for Windows on Arm on BUILD.bazel along with proper Volterra detection (#220)\n\nThis MR includes support for building with Bazel  on cpu `arm64_windows`, I also tried this on my Volterra Windows Dev Kit and noticed that the core string seems different from what the current source code defines. I don't know if this is because my hardware is a bit different or not. \r\n\r\nI ran the tests with the following results\r\n\r\n```\r\n[==========] Running 132 tests from 28 test suites.\r\n[----------] Global test environment set-up.\r\n[----------] 1 test from PROCESSORS_COUNT\r\n[ RUN      ] PROCESSORS_COUNT.non_zero\r\n[       OK ] PROCESSORS_COUNT.non_zero (0 ms)\r\n[----------] 1 test from PROCESSORS_COUNT (0 ms total)\r\n\r\n[----------] 1 test from PROCESSORS\r\n[ RUN      ] PROCESSORS.non_null\r\n[       OK ] PROCESSORS.non_null (0 ms)\r\n[----------] 1 test from PROCESSORS (0 ms total)\r\n\r\n[----------] 13 tests from PROCESSOR\r\n[ RUN      ] PROCESSOR.non_null\r\n[       OK ] PROCESSOR.non_null (0 ms)\r\n[ RUN      ] PROCESSOR.valid_smt_id\r\n[       OK ] PROCESSOR.valid_smt_id (0 ms)\r\n[ RUN      ] PROCESSOR.valid_core\r\n[       OK ] PROCESSOR.valid_core (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_core\r\n[       OK ] PROCESSOR.consistent_core (0 ms)\r\n[ RUN      ] PROCESSOR.valid_cluster\r\n[       OK ] PROCESSOR.valid_cluster (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_cluster\r\n[       OK ] PROCESSOR.consistent_cluster (0 ms)\r\n[ RUN      ] PROCESSOR.valid_package\r\n[       OK ] PROCESSOR.valid_package (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_package\r\n[       OK ] PROCESSOR.consistent_package (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_l1i\r\n[       OK ] PROCESSOR.consistent_l1i (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_l1d\r\n[       OK ] PROCESSOR.consistent_l1d (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_l2\r\n[       OK ] PROCESSOR.consistent_l2 (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_l3\r\n[       OK ] PROCESSOR.consistent_l3 (0 ms)\r\n[ RUN      ] PROCESSOR.consistent_l4\r\n[       OK ] PROCESSOR.consistent_l4 (0 ms)\r\n[----------] 13 tests from PROCESSOR (7 ms total)\r\n\r\n[----------] 1 test from CORES_COUNT\r\n[ RUN      ] CORES_COUNT.within_bounds\r\n[       OK ] CORES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from CORES_COUNT (0 ms total)\r\n\r\n[----------] 1 test from CORES\r\n[ RUN      ] CORES.non_null\r\n[       OK ] CORES.non_null (0 ms)\r\n[----------] 1 test from CORES (0 ms total)\r\n\r\n[----------] 10 tests from CORE\r\n[ RUN      ] CORE.non_null\r\n[       OK ] CORE.non_null (0 ms)\r\n[ RUN      ] CORE.non_zero_processors\r\n[       OK ] CORE.non_zero_processors (0 ms)\r\n[ RUN      ] CORE.consistent_processors\r\n[       OK ] CORE.consistent_processors (0 ms)\r\n[ RUN      ] CORE.valid_core_id\r\n[       OK ] CORE.valid_core_id (0 ms)\r\n[ RUN      ] CORE.valid_cluster\r\n[       OK ] CORE.valid_cluster (0 ms)\r\n[ RUN      ] CORE.consistent_cluster\r\n[       OK ] CORE.consistent_cluster (0 ms)\r\n[ RUN      ] CORE.valid_package\r\n[       OK ] CORE.valid_package (0 ms)\r\n[ RUN      ] CORE.consistent_package\r\n[       OK ] CORE.consistent_package (0 ms)\r\n[ RUN      ] CORE.known_vendor\r\n[       OK ] CORE.known_vendor (0 ms)\r\n[ RUN      ] CORE.known_uarch\r\n[       OK ] CORE.known_uarch (0 ms)\r\n[----------] 10 tests from CORE (5 ms total)\r\n\r\n[----------] 1 test from CLUSTERS_COUNT\r\n[ RUN      ] CLUSTERS_COUNT.within_bounds\r\n[       OK ] CLUSTERS_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from CLUSTERS_COUNT (0 ms total)\r\n\r\n[----------] 1 test from CLUSTERS\r\n[ RUN      ] CLUSTERS.non_null\r\n[       OK ] CLUSTERS.non_null (0 ms)\r\n[----------] 1 test from CLUSTERS (0 ms total)\r\n\r\n[----------] 14 tests from CLUSTER\r\n[ RUN      ] CLUSTER.non_null\r\n[       OK ] CLUSTER.non_null (0 ms)\r\n[ RUN      ] CLUSTER.non_zero_processors\r\n[       OK ] CLUSTER.non_zero_processors (0 ms)\r\n[ RUN      ] CLUSTER.valid_processors\r\n[       OK ] CLUSTER.valid_processors (0 ms)\r\n[ RUN      ] CLUSTER.consistent_processors\r\n[       OK ] CLUSTER.consistent_processors (0 ms)\r\n[ RUN      ] CLUSTER.non_zero_cores\r\n[       OK ] CLUSTER.non_zero_cores (0 ms)\r\n[ RUN      ] CLUSTER.valid_cores\r\n[       OK ] CLUSTER.valid_cores (0 ms)\r\n[ RUN      ] CLUSTER.consistent_cores\r\n[       OK ] CLUSTER.consistent_cores (0 ms)\r\n[ RUN      ] CLUSTER.valid_cluster_id\r\n[       OK ] CLUSTER.valid_cluster_id (0 ms)\r\n[ RUN      ] CLUSTER.valid_package\r\n[       OK ] CLUSTER.valid_package (0 ms)\r\n[ RUN      ] CLUSTER.consistent_package\r\n[       OK ] CLUSTER.consistent_package (0 ms)\r\n[ RUN      ] CLUSTER.consistent_vendor\r\n[       OK ] CLUSTER.consistent_vendor (0 ms)\r\n[ RUN      ] CLUSTER.consistent_uarch\r\n[       OK ] CLUSTER.consistent_uarch (0 ms)\r\n[ RUN      ] CLUSTER.consistent_midr\r\n[       OK ] CLUSTER.consistent_midr (0 ms)\r\n[ RUN      ] CLUSTER.consistent_frequency\r\n[       OK ] CLUSTER.consistent_frequency (0 ms)\r\n[----------] 14 tests from CLUSTER (7 ms total)\r\n\r\n[----------] 1 test from PACKAGES_COUNT\r\n[ RUN      ] PACKAGES_COUNT.within_bounds\r\n[       OK ] PACKAGES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from PACKAGES_COUNT (0 ms total)\r\n\r\n[----------] 1 test from PACKAGES\r\n[ RUN      ] PACKAGES.non_null\r\n[       OK ] PACKAGES.non_null (0 ms)\r\n[----------] 1 test from PACKAGES (0 ms total)\r\n\r\n[----------] 10 tests from PACKAGE\r\n[ RUN      ] PACKAGE.non_null\r\n[       OK ] PACKAGE.non_null (0 ms)\r\n[ RUN      ] PACKAGE.non_zero_processors\r\n[       OK ] PACKAGE.non_zero_processors (0 ms)\r\n[ RUN      ] PACKAGE.valid_processors\r\n[       OK ] PACKAGE.valid_processors (0 ms)\r\n[ RUN      ] PACKAGE.consistent_processors\r\n[       OK ] PACKAGE.consistent_processors (0 ms)\r\n[ RUN      ] PACKAGE.non_zero_cores\r\n[       OK ] PACKAGE.non_zero_cores (0 ms)\r\n[ RUN      ] PACKAGE.valid_cores\r\n[       OK ] PACKAGE.valid_cores (0 ms)\r\n[ RUN      ] PACKAGE.consistent_cores\r\n[       OK ] PACKAGE.consistent_cores (0 ms)\r\n[ RUN      ] PACKAGE.non_zero_clusters\r\n[       OK ] PACKAGE.non_zero_clusters (0 ms)\r\n[ RUN      ] PACKAGE.valid_clusters\r\n[       OK ] PACKAGE.valid_clusters (0 ms)\r\n[ RUN      ] PACKAGE.consistent_cluster\r\n[       OK ] PACKAGE.consistent_cluster (0 ms)\r\n[----------] 10 tests from PACKAGE (5 ms total)\r\n\r\n[----------] 1 test from UARCHS_COUNT\r\n[ RUN      ] UARCHS_COUNT.within_bounds\r\n[       OK ] UARCHS_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from UARCHS_COUNT (0 ms total)\r\n\r\n[----------] 1 test from UARCHS\r\n[ RUN      ] UARCHS.non_null\r\n[       OK ] UARCHS.non_null (0 ms)\r\n[----------] 1 test from UARCHS (0 ms total)\r\n\r\n[----------] 5 tests from UARCH\r\n[ RUN      ] UARCH.non_null\r\n[       OK ] UARCH.non_null (0 ms)\r\n[ RUN      ] UARCH.non_zero_processors\r\n[       OK ] UARCH.non_zero_processors (0 ms)\r\n[ RUN      ] UARCH.valid_processors\r\n[       OK ] UARCH.valid_processors (0 ms)\r\n[ RUN      ] UARCH.non_zero_cores\r\n[       OK ] UARCH.non_zero_cores (0 ms)\r\n[ RUN      ] UARCH.valid_cores\r\n[       OK ] UARCH.valid_cores (0 ms)\r\n[----------] 5 tests from UARCH (2 ms total)\r\n\r\n[----------] 1 test from L1I_CACHES_COUNT\r\n[ RUN      ] L1I_CACHES_COUNT.within_bounds\r\n[       OK ] L1I_CACHES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from L1I_CACHES_COUNT (0 ms total)\r\n\r\n[----------] 1 test from L1I_CACHES\r\n[ RUN      ] L1I_CACHES.non_null\r\n[       OK ] L1I_CACHES.non_null (0 ms)\r\n[----------] 1 test from L1I_CACHES (0 ms total)\r\n\r\n[----------] 13 tests from L1I_CACHE\r\n[ RUN      ] L1I_CACHE.non_null\r\n[       OK ] L1I_CACHE.non_null (0 ms)\r\n[ RUN      ] L1I_CACHE.non_zero_size\r\n[       OK ] L1I_CACHE.non_zero_size (0 ms)\r\n[ RUN      ] L1I_CACHE.valid_size\r\n[       OK ] L1I_CACHE.valid_size (0 ms)\r\n[ RUN      ] L1I_CACHE.non_zero_associativity\r\n[       OK ] L1I_CACHE.non_zero_associativity (0 ms)\r\n[ RUN      ] L1I_CACHE.non_zero_partitions\r\n[       OK ] L1I_CACHE.non_zero_partitions (0 ms)\r\n[ RUN      ] L1I_CACHE.non_zero_line_size\r\n[       OK ] L1I_CACHE.non_zero_line_size (0 ms)\r\n[ RUN      ] L1I_CACHE.power_of_2_line_size\r\n[       OK ] L1I_CACHE.power_of_2_line_size (0 ms)\r\n[ RUN      ] L1I_CACHE.reasonable_line_size\r\n[       OK ] L1I_CACHE.reasonable_line_size (0 ms)\r\n[ RUN      ] L1I_CACHE.valid_flags\r\n[       OK ] L1I_CACHE.valid_flags (0 ms)\r\n[ RUN      ] L1I_CACHE.non_inclusive\r\n[       OK ] L1I_CACHE.non_inclusive (0 ms)\r\n[ RUN      ] L1I_CACHE.non_zero_processors\r\n[       OK ] L1I_CACHE.non_zero_processors (0 ms)\r\n[ RUN      ] L1I_CACHE.valid_processors\r\n[       OK ] L1I_CACHE.valid_processors (0 ms)\r\n[ RUN      ] L1I_CACHE.consistent_processors\r\n[       OK ] L1I_CACHE.consistent_processors (0 ms)\r\n[----------] 13 tests from L1I_CACHE (7 ms total)\r\n\r\n[----------] 1 test from L1D_CACHES_COUNT\r\n[ RUN      ] L1D_CACHES_COUNT.within_bounds\r\n[       OK ] L1D_CACHES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from L1D_CACHES_COUNT (0 ms total)\r\n\r\n[----------] 1 test from L1D_CACHES\r\n[ RUN      ] L1D_CACHES.non_null\r\n[       OK ] L1D_CACHES.non_null (0 ms)\r\n[----------] 1 test from L1D_CACHES (0 ms total)\r\n\r\n[----------] 13 tests from L1D_CACHE\r\n[ RUN      ] L1D_CACHE.non_null\r\n[       OK ] L1D_CACHE.non_null (0 ms)\r\n[ RUN      ] L1D_CACHE.non_zero_size\r\n[       OK ] L1D_CACHE.non_zero_size (0 ms)\r\n[ RUN      ] L1D_CACHE.valid_size\r\n[       OK ] L1D_CACHE.valid_size (0 ms)\r\n[ RUN      ] L1D_CACHE.non_zero_associativity\r\n[       OK ] L1D_CACHE.non_zero_associativity (0 ms)\r\n[ RUN      ] L1D_CACHE.non_zero_partitions\r\n[       OK ] L1D_CACHE.non_zero_partitions (0 ms)\r\n[ RUN      ] L1D_CACHE.non_zero_line_size\r\n[       OK ] L1D_CACHE.non_zero_line_size (0 ms)\r\n[ RUN      ] L1D_CACHE.power_of_2_line_size\r\n[       OK ] L1D_CACHE.power_of_2_line_size (0 ms)\r\n[ RUN      ] L1D_CACHE.reasonable_line_size\r\n[       OK ] L1D_CACHE.reasonable_line_size (0 ms)\r\n[ RUN      ] L1D_CACHE.valid_flags\r\n[       OK ] L1D_CACHE.valid_flags (0 ms)\r\n[ RUN      ] L1D_CACHE.non_inclusive\r\n[       OK ] L1D_CACHE.non_inclusive (0 ms)\r\n[ RUN      ] L1D_CACHE.non_zero_processors\r\n[       OK ] L1D_CACHE.non_zero_processors (0 ms)\r\n[ RUN      ] L1D_CACHE.valid_processors\r\n[       OK ] L1D_CACHE.valid_processors (0 ms)\r\n[ RUN      ] L1D_CACHE.consistent_processors\r\n[       OK ] L1D_CACHE.consistent_processors (0 ms)\r\n[----------] 13 tests from L1D_CACHE (7 ms total)\r\n\r\n[----------] 1 test from L2_CACHES_COUNT\r\n[ RUN      ] L2_CACHES_COUNT.within_bounds\r\n[       OK ] L2_CACHES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from L2_CACHES_COUNT (0 ms total)\r\n\r\n[----------] 1 test from L2_CACHES\r\n[ RUN      ] L2_CACHES.non_null\r\n[       OK ] L2_CACHES.non_null (0 ms)\r\n[----------] 1 test from L2_CACHES (0 ms total)\r\n\r\n[----------] 12 tests from L2_CACHE\r\n[ RUN      ] L2_CACHE.non_null\r\n[       OK ] L2_CACHE.non_null (0 ms)\r\n[ RUN      ] L2_CACHE.non_zero_size\r\n[       OK ] L2_CACHE.non_zero_size (0 ms)\r\n[ RUN      ] L2_CACHE.valid_size\r\n[       OK ] L2_CACHE.valid_size (0 ms)\r\n[ RUN      ] L2_CACHE.non_zero_associativity\r\n[       OK ] L2_CACHE.non_zero_associativity (0 ms)\r\n[ RUN      ] L2_CACHE.non_zero_partitions\r\n[       OK ] L2_CACHE.non_zero_partitions (0 ms)\r\n[ RUN      ] L2_CACHE.non_zero_line_size\r\n[       OK ] L2_CACHE.non_zero_line_size (0 ms)\r\n[ RUN      ] L2_CACHE.power_of_2_line_size\r\n[       OK ] L2_CACHE.power_of_2_line_size (0 ms)\r\n[ RUN      ] L2_CACHE.reasonable_line_size\r\n[       OK ] L2_CACHE.reasonable_line_size (0 ms)\r\n[ RUN      ] L2_CACHE.valid_flags\r\n[       OK ] L2_CACHE.valid_flags (0 ms)\r\n[ RUN      ] L2_CACHE.non_zero_processors\r\n[       OK ] L2_CACHE.non_zero_processors (0 ms)\r\n[ RUN      ] L2_CACHE.valid_processors\r\n[       OK ] L2_CACHE.valid_processors (0 ms)\r\n[ RUN      ] L2_CACHE.consistent_processors\r\n[       OK ] L2_CACHE.consistent_processors (0 ms)\r\n[----------] 12 tests from L2_CACHE (6 ms total)\r\n\r\n[----------] 1 test from L3_CACHES_COUNT\r\n[ RUN      ] L3_CACHES_COUNT.within_bounds\r\n[       OK ] L3_CACHES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from L3_CACHES_COUNT (0 ms total)\r\n\r\n[----------] 12 tests from L3_CACHE\r\n[ RUN      ] L3_CACHE.non_null\r\n[       OK ] L3_CACHE.non_null (0 ms)\r\n[ RUN      ] L3_CACHE.non_zero_size\r\n[       OK ] L3_CACHE.non_zero_size (0 ms)\r\n[ RUN      ] L3_CACHE.valid_size\r\n[       OK ] L3_CACHE.valid_size (0 ms)\r\n[ RUN      ] L3_CACHE.non_zero_associativity\r\n[       OK ] L3_CACHE.non_zero_associativity (0 ms)\r\n[ RUN      ] L3_CACHE.non_zero_partitions\r\n[       OK ] L3_CACHE.non_zero_partitions (0 ms)\r\n[ RUN      ] L3_CACHE.non_zero_line_size\r\n[       OK ] L3_CACHE.non_zero_line_size (0 ms)\r\n[ RUN      ] L3_CACHE.power_of_2_line_size\r\n[       OK ] L3_CACHE.power_of_2_line_size (0 ms)\r\n[ RUN      ] L3_CACHE.reasonable_line_size\r\n[       OK ] L3_CACHE.reasonable_line_size (0 ms)\r\n[ RUN      ] L3_CACHE.valid_flags\r\n[       OK ] L3_CACHE.valid_flags (0 ms)\r\n[ RUN      ] L3_CACHE.non_zero_processors\r\n[       OK ] L3_CACHE.non_zero_processors (0 ms)\r\n[ RUN      ] L3_CACHE.valid_processors\r\n[       OK ] L3_CACHE.valid_processors (0 ms)\r\n[ RUN      ] L3_CACHE.consistent_processors\r\n[       OK ] L3_CACHE.consistent_processors (0 ms)\r\n[----------] 12 tests from L3_CACHE (6 ms total)\r\n\r\n[----------] 1 test from L4_CACHES_COUNT\r\n[ RUN      ] L4_CACHES_COUNT.within_bounds\r\n[       OK ] L4_CACHES_COUNT.within_bounds (0 ms)\r\n[----------] 1 test from L4_CACHES_COUNT (0 ms total)\r\n\r\n[----------] 12 tests from L4_CACHE\r\n[ RUN      ] L4_CACHE.non_null\r\n[       OK ] L4_CACHE.non_null (0 ms)\r\n[ RUN      ] L4_CACHE.non_zero_size\r\n[       OK ] L4_CACHE.non_zero_size (0 ms)\r\n[ RUN      ] L4_CACHE.valid_size\r\n[       OK ] L4_CACHE.valid_size (0 ms)\r\n[ RUN      ] L4_CACHE.non_zero_associativity\r\n[       OK ] L4_CACHE.non_zero_associativity (0 ms)\r\n[ RUN      ] L4_CACHE.non_zero_partitions\r\n[       OK ] L4_CACHE.non_zero_partitions (0 ms)\r\n[ RUN      ] L4_CACHE.non_zero_line_size\r\n[       OK ] L4_CACHE.non_zero_line_size (0 ms)\r\n[ RUN      ] L4_CACHE.power_of_2_line_size\r\n[       OK ] L4_CACHE.power_of_2_line_size (0 ms)\r\n[ RUN      ] L4_CACHE.reasonable_line_size\r\n[       OK ] L4_CACHE.reasonable_line_size (0 ms)\r\n[ RUN      ] L4_CACHE.valid_flags\r\n[       OK ] L4_CACHE.valid_flags (0 ms)\r\n[ RUN      ] L4_CACHE.non_zero_processors\r\n[       OK ] L4_CACHE.non_zero_processors (0 ms)\r\n[ RUN      ] L4_CACHE.valid_processors\r\n[       OK ] L4_CACHE.valid_processors (0 ms)\r\n[ RUN      ] L4_CACHE.consistent_processors\r\n[       OK ] L4_CACHE.consistent_processors (0 ms)\r\n[----------] 12 tests from L4_CACHE (6 ms total)\r\n\r\n[----------] Global test environment tear-down\r\n[==========] 132 tests from 28 test suites ran. (93 ms total)\r\n[  PASSED  ] 132 tests.\r\n```\r\n\r\nwith `cpu-info.exe` returning\r\n\r\n```\r\nPackages:\r\n        0: Snapdragon (TM) 8cx Gen 3\r\nMicroarchitectures:\r\n        4x Cortex-A78\r\n        4x Cortex-X1\r\nCores:\r\n        0: 1 processor (0), ARM Cortex-A78\r\n        1: 1 processor (1), ARM Cortex-A78\r\n        2: 1 processor (2), ARM Cortex-A78\r\n        3: 1 processor (3), ARM Cortex-A78\r\n        4: 1 processor (4), ARM Cortex-X1\r\n        5: 1 processor (5), ARM Cortex-X1\r\n        6: 1 processor (6), ARM Cortex-X1\r\n        7: 1 processor (7), ARM Cortex-X1\r\nLogical processors:\r\n        0\r\n        1\r\n        2\r\n        3\r\n        4\r\n        5\r\n        6\r\n        7\r\n```\r\n\r\nand `isa-info.exe` returning\r\n\r\n```\r\nInstruction sets:\r\n        ARM v8.1 atomics: yes\r\n        ARM v8.1 SQRDMLxH: yes\r\n        ARM v8.2 FP16 arithmetics: yes\r\n        ARM v8.2 FHM: no\r\n        ARM v8.2 BF16: no\r\n        ARM v8.2 Int8 dot product: yes\r\n        ARM v8.2 Int8 matrix multiplication: no\r\n        ARM v8.3 JS conversion: no\r\n        ARM v8.3 complex: no\r\nSIMD extensions:\r\n        ARM SVE: no\r\n        ARM SVE 2: no\r\nCryptography extensions:\r\n        AES: yes\r\n        SHA1: yes\r\n        SHA2: yes\r\n        PMULL: yes\r\n        CRC32: yes\r\n```","shortMessageHtmlLink":"Include support for Windows on Arm on BUILD.bazel along with proper V…"}},{"before":"aa4b2163b99ac9534194520f70b93eeefb0b3b4e","after":"fb08ae018ef8d8f71e3a2960c0982f90b688fe06","ref":"refs/heads/main","pushedAt":"2024-03-15T15:43:54.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Bazel-support: Add MODUEL.bazel to support Bzlmod (#229)\n\nThis PR adds a `MODULE.bazel` file. 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In the meantime, both files are needed.","shortMessageHtmlLink":"Bazel-support: Add MODUEL.bazel to support Bzlmod (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2177809166\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/229\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/229/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/229\">#229</a>)"}},{"before":"9484a6c590f831a30c1eec1311568b1a967a89dc","after":"aa4b2163b99ac9534194520f70b93eeefb0b3b4e","ref":"refs/heads/main","pushedAt":"2024-02-26T15:33:39.000Z","pushType":"pr_merge","commitsCount":2,"pusher":{"login":"digantdesai","name":"Digant Desai","path":"/digantdesai","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/368720?s=80&v=4"},"commit":{"message":"Merge pull request #225 from fbarchard/break\n\ncachebreak","shortMessageHtmlLink":"Merge pull request <a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2152021442\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/225\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/225/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/225\">#225</a> from fbarchard/break"}},{"before":"434970b5d072d2f1e5e5fb44009884f278514588","after":"9484a6c590f831a30c1eec1311568b1a967a89dc","ref":"refs/heads/main","pushedAt":"2024-01-23T14:59:49.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"ci: Add an Ubuntu:22.04 builder for RISC-V (#219)\n\ncpuinfo is built for riscv64 using a riscv64 container.  binfmt_misc\r\nallows the riscv64 binaries in the container to be executed with QEMU.\r\nThis is slower than cross compiling but as there's not that much code\r\nthe build times are acceptable.  It takes just under 6 minutes for the\r\nfull riscv64 github action to run.  We also have the option of running\r\nsome of the built RISC-V binaries, e.g., unit tests, in the CI. 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We\r\nfix the issue by only including sys/hwprobe.h when building for\r\nAndroid, and invoking the hwprobe syscall directly on other\r\nLinux distributions.  The Android specific check can be removed in\r\nthe future once sys/hwprobe.h becomes available in glibc.","shortMessageHtmlLink":"Fix RISC-V Linux build (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"2038597137\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/212\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/212/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/212\">#212</a>)"}},{"before":"b8b29a164e7704b75ad66b072aa2db409cc941fd","after":"2f4c278f7aa3e9a451c14c3e9a02c3e091140d96","ref":"refs/heads/main","pushedAt":"2023-12-08T05:34:03.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Improve smallfile callback (#211)\n\nThis PR improves the smallfile callback error reporting, passing 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Adds ISA information for RISC-V and hwcap support.\r\n\r\n* Adds support to construct the processor, core, cluster and package\r\n  information reported by the system.\r\n\r\n* Remaining support required for:\r\n  - Inferring uarch of each processor (reports unknown for now).\r\n  - Reading cache information (left empty for now).\r\n\r\nTest: Build and ran cpu_info and isa_info on RISC-V QEMU instance and\r\nRISC-V Android emulator. Confirmed that it properly reports the ISA\r\ninformation as well as processor and cluster counts.","shortMessageHtmlLink":"Add limited support for RISC-V initialization (<a class=\"issue-link js-issue-link\" data-error-text=\"Failed to load title\" data-id=\"1865264002\" data-permission-text=\"Title is private\" data-url=\"https://github.com/pytorch/cpuinfo/issues/190\" data-hovercard-type=\"pull_request\" data-hovercard-url=\"/pytorch/cpuinfo/pull/190/hovercard\" href=\"https://github.com/pytorch/cpuinfo/pull/190\">#190</a>)"}},{"before":"76d5e8f5b563daa65340a60fce0e9aec73a936df","after":"d6860c477c99f1fce9e28eb206891af3c0e1a1d7","ref":"refs/heads/main","pushedAt":"2023-11-04T00:50:14.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"malfet","name":"Nikita Shulga","path":"/malfet","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/2453524?s=80&v=4"},"commit":{"message":"Add detection of Intel x86 AVX-VNNI instructions. (#196)\n\nTested using Intel SDE:\r\n\r\n```\r\nbash scripts/local-build.sh\r\n\r\nOPTIONS=()\r\nPLATFORMS=()\r\n\r\nOPTIONS+=(-quark); PLATFORMS+=(\"Quark\")\r\nOPTIONS+=(-p4); PLATFORMS+=(\"Pentium4\")\r\nOPTIONS+=(-p4p); PLATFORMS+=(\"Pentium4 Prescott\")\r\nOPTIONS+=(-mrm); PLATFORMS+=(\"Merom\")\r\nOPTIONS+=(-pnr); PLATFORMS+=(\"Penryn\")\r\nOPTIONS+=(-nhm); PLATFORMS+=(\"Nehalem\")\r\nOPTIONS+=(-wsm); PLATFORMS+=(\"Westmere\")\r\nOPTIONS+=(-snb); PLATFORMS+=(\"Sandy Bridge\")\r\nOPTIONS+=(-ivb); PLATFORMS+=(\"Ivy Bridge\")\r\nOPTIONS+=(-hsw); PLATFORMS+=(\"Haswell\")\r\nOPTIONS+=(-bdw); PLATFORMS+=(\"Broadwell\")\r\nOPTIONS+=(-slt); PLATFORMS+=(\"Saltwell\")\r\nOPTIONS+=(-slm); PLATFORMS+=(\"Silvermont\")\r\nOPTIONS+=(-glm); PLATFORMS+=(\"Goldmont\")\r\nOPTIONS+=(-glp); PLATFORMS+=(\"Goldmont Plus\")\r\nOPTIONS+=(-tnt); PLATFORMS+=(\"Tremont\")\r\nOPTIONS+=(-snr); PLATFORMS+=(\"Snow Ridge\")\r\nOPTIONS+=(-skl); PLATFORMS+=(\"Skylake\")\r\nOPTIONS+=(-cnl); PLATFORMS+=(\"Cannon Lake\")\r\nOPTIONS+=(-icl); PLATFORMS+=(\"Ice Lake\")\r\nOPTIONS+=(-skx); PLATFORMS+=(\"Skylake server\")\r\nOPTIONS+=(-clx); PLATFORMS+=(\"Cascade Lake\")\r\nOPTIONS+=(-cpx); PLATFORMS+=(\"Cooper Lake\")\r\nOPTIONS+=(-icx); PLATFORMS+=(\"Ice Lake server\")\r\nOPTIONS+=(-knl); PLATFORMS+=(\"Knights landing\")\r\nOPTIONS+=(-knm); PLATFORMS+=(\"Knights mill\")\r\nOPTIONS+=(-tgl); PLATFORMS+=(\"Tiger Lake\")\r\nOPTIONS+=(-adl); PLATFORMS+=(\"Alder Lake\")\r\nOPTIONS+=(-mtl); PLATFORMS+=(\"Meteor Lake\")\r\nOPTIONS+=(-rpl); PLATFORMS+=(\"Raptor Lake\")\r\nOPTIONS+=(-spr); PLATFORMS+=(\"Sapphire Rapids\")\r\nOPTIONS+=(-gnr); PLATFORMS+=(\"Granite Rapids\")\r\nOPTIONS+=(-srf); PLATFORMS+=(\"Sierra Forest\")\r\nOPTIONS+=(-grr); PLATFORMS+=(\"Grand Ridge\")\r\nOPTIONS+=(-future); PLATFORMS+=(\"Future chip\")\r\n\r\nSDE_BIN=\"path/to/sde\"\r\n\r\nfor I in \"${!PLATFORMS[@]}\"; do\r\n  echo \"${PLATFORMS[\"${I}\"]}\"\r\n  \"${SDE_BIN}\" \"${OPTIONS[$I]}\" -- ./build/local/isa-info | grep \"AVXVNNI\"\r\ndone\r\n```\r\n\r\nResult:\r\n\r\n```\r\nQuark\r\n        [error]\r\nMerom\r\n        [error]\r\nPenryn\r\n        [error]\r\nNehalem\r\n        [error]\r\nWestmere\r\n        AVXVNNI: no\r\nSandy Bridge\r\n        AVXVNNI: no\r\nIvy Bridge\r\n        AVXVNNI: no\r\nHaswell\r\n        AVXVNNI: no\r\nBroadwell\r\n        AVXVNNI: no\r\nSaltwell\r\n        [error]\r\nSilvermont\r\n        AVXVNNI: no\r\nGoldmont\r\n        AVXVNNI: no\r\nGoldmont Plus\r\n        AVXVNNI: no\r\nTremont\r\n        AVXVNNI: no\r\nSnow Ridge\r\n        AVXVNNI: no\r\nSkylake\r\n        AVXVNNI: no\r\nCannon Lake\r\n        AVXVNNI: no\r\nIce Lake\r\n        AVXVNNI: no\r\nSkylake server\r\n        AVXVNNI: no\r\nCascade Lake\r\n        AVXVNNI: no\r\nCooper Lake\r\n        AVXVNNI: no\r\nIce Lake server\r\n        AVXVNNI: no\r\nKnights landing\r\n        AVXVNNI: no\r\nKnights mill\r\n        AVXVNNI: no\r\nTiger Lake\r\n        AVXVNNI: no\r\nAlder Lake\r\n        AVXVNNI: yes\r\nMeteor Lake\r\n        AVXVNNI: yes\r\nRaptor Lake\r\n        AVXVNNI: yes\r\nSapphire Rapids\r\n        AVXVNNI: yes\r\nGranite Rapids\r\n        AVXVNNI: yes\r\nSierra Forest\r\n        AVXVNNI: yes\r\nGrand Ridge\r\n        AVXVNNI: yes\r\nFuture chip\r\n        AVXVNNI: yes\r\n```","shortMessageHtmlLink":"Add detection of Intel x86 AVX-VNNI instructions. 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