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bcm2835.h
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bcm2835.h
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/* bcm2835.h
C and C++ support for Broadcom BCM 2835 as used in Raspberry Pi
Author: Mike McCauley
Copyright (C) 2011-2013 Mike McCauley
$Id: bcm2835.h,v 1.20 2015/03/31 04:55:41 mikem Exp mikem $
*/
/*! \mainpage C library for Broadcom BCM 2835 as used in Raspberry Pi
This is a C library for Raspberry Pi (RPi). It provides access to
GPIO and other IO functions on the Broadcom BCM 2835 chip,
allowing access to the GPIO pins on the
26 pin IDE plug on the RPi board so you can control and interface with various external devices.
It provides functions for reading digital inputs and setting digital outputs, using SPI and I2C,
and for accessing the system timers.
Pin event detection is supported by polling (interrupts are not supported).
It is C++ compatible, and installs as a header file and non-shared library on
any Linux-based distro (but clearly is no use except on Raspberry Pi or another board with
BCM 2835).
The version of the package that this documentation refers to can be downloaded
from http://www.airspayce.com/mikem/bcm2835/bcm2835-1.50.tar.gz
You can find the latest version at http://www.airspayce.com/mikem/bcm2835
Several example programs are provided.
Based on data in http://elinux.org/RPi_Low-level_peripherals and
http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
and http://www.scribd.com/doc/101830961/GPIO-Pads-Control2
You can also find online help and discussion at http://groups.google.com/group/bcm2835
Please use that group for all questions and discussions on this topic.
Do not contact the author directly, unless it is to discuss commercial licensing.
Before asking a question or reporting a bug, please read http://www.catb.org/esr/faqs/smart-questions.html
Tested on debian6-19-04-2012, 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian
and Occidentalisv01, 2016-02-09 Raspbian Jessie.
CAUTION: it has been observed that when detect enables such as bcm2835_gpio_len()
are used and the pin is pulled LOW
it can cause temporary hangs on 2012-07-15-wheezy-raspbian, 2013-07-26-wheezy-raspbian
and Occidentalisv01.
Reason for this is not yet determined, but we suspect that an interrupt handler is
hitting a hard loop on those OSs.
If you must use bcm2835_gpio_len() and friends, make sure you disable the pins with
bcm2835_gpio_clr_len() and friends after use.
\par Running as root
Prior to the release of Raspbian Jessie in Feb 2016, access to any
peripheral device via /dev/mem on the RPi required the process to
run as root. Raspbian Jessie permits non-root users to access the
GPIO peripheral (only) via /dev/gpiomem, and this library supports
that limited mode of operation.
If the library runs with effective UID of 0 (ie root), then
bcm2835_init() will attempt to open /dev/mem, and, if successful, it
will permit use of all peripherals and library functions.
If the library runs with any other effective UID (ie not root), then
bcm2835_init() will attempt to open /dev/gpiomem, and, if
successful, will only permit GPIO operations. In particular,
bcm2835_spi_begin() and bcm2835_i2c_begin() will return false and all
other non-gpio operations may fail silently or crash.
\par Installation
This library consists of a single non-shared library and header file, which will be
installed in the usual places by make install
\code
# download the latest version of the library, say bcm2835-1.xx.tar.gz, then:
tar zxvf bcm2835-1.xx.tar.gz
cd bcm2835-1.xx
./configure
make
sudo make check
sudo make install
\endcode
\par Physical Addresses
The functions bcm2835_peri_read(), bcm2835_peri_write() and bcm2835_peri_set_bits()
are low level peripheral register access functions. They are designed to use
physical addresses as described in section 1.2.3 ARM physical addresses
of the BCM2835 ARM Peripherals manual.
Physical addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus
addresses for peripherals are set up to map onto the peripheral bus address range starting at
0x7E000000. Thus a peripheral advertised in the manual at bus address 0x7Ennnnnn is available at
physical address 0x20nnnnnn.
On RPI 2, the peripheral addresses are different and the bcm2835 library gets them
from reading /proc/device-tree/soc/ranges. This is only availble with recent versions of the kernel on RPI 2.
After initialisation, the base address of the various peripheral
registers are available with the following
externals:
bcm2835_gpio
bcm2835_pwm
bcm2835_clk
bcm2835_pads
bcm2835_spio0
bcm2835_st
bcm2835_bsc0
bcm2835_bsc1
\par Raspberry Pi 2 (RPI2)
For this library to work correctly on RPI2, you MUST have the device tree support enabled in the kernel.
You should also ensure you are using the latest version of Linux. The library has been tested on RPI2
with 2015-02-16-raspbian-wheezy and ArchLinuxARM-rpi-2 as of 2015-03-29.
When device tree suport is enabled, the file /proc/device-tree/soc/ranges will appear in the file system,
and the bcm2835 module relies on its presence to correctly run on RPI2 (it is optional for RPI1).
Without device tree support enabled and the presence of this file, it will not work on RPI2.
To enable device tree support:
\code
sudo raspi-config
under Advanced Options - enable Device Tree
Reboot.
\endcode
\par Pin Numbering
The GPIO pin numbering as used by RPi is different to and inconsistent with the underlying
BCM 2835 chip pin numbering. http://elinux.org/RPi_BCM2835_GPIOs
RPi has a 26 pin IDE header that provides access to some of the GPIO pins on the BCM 2835,
as well as power and ground pins. Not all GPIO pins on the BCM 2835 are available on the
IDE header.
RPi Version 2 also has a P5 connector with 4 GPIO pins, 5V, 3.3V and Gnd.
The functions in this library are designed to be passed the BCM 2835 GPIO pin number and _not_
the RPi pin number. There are symbolic definitions for each of the available pins
that you should use for convenience. See \ref RPiGPIOPin.
\par SPI Pins
The bcm2835_spi_* functions allow you to control the BCM 2835 SPI0 interface,
allowing you to send and received data by SPI (Serial Peripheral Interface).
For more information about SPI, see http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
When bcm2835_spi_begin() is called it changes the bahaviour of the SPI interface pins from their
default GPIO behaviour in order to support SPI. While SPI is in use, you will not be able
to control the state of the SPI pins through the usual bcm2835_spi_gpio_write().
When bcm2835_spi_end() is called, the SPI pins will all revert to inputs, and can then be
configured and controled with the usual bcm2835_gpio_* calls.
The Raspberry Pi GPIO pins used for SPI are:
- P1-19 (MOSI)
- P1-21 (MISO)
- P1-23 (CLK)
- P1-24 (CE0)
- P1-26 (CE1)
\par I2C Pins
The bcm2835_i2c_* functions allow you to control the BCM 2835 BSC interface,
allowing you to send and received data by I2C ("eye-squared cee"; generically referred to as "two-wire interface") .
For more information about I?C, see http://en.wikipedia.org/wiki/I%C2%B2C
The Raspberry Pi V2 GPIO pins used for I2C are:
- P1-03 (SDA)
- P1-05 (SLC)
\par PWM
The BCM2835 supports hardware PWM on a limited subset of GPIO pins. This bcm2835 library provides
functions for configuring and controlling PWM output on these pins.
The BCM2835 contains 2 independent PWM channels (0 and 1), each of which be connnected to a limited subset of
GPIO pins. The following GPIO pins may be connected to the following PWM channels (from section 9.5):
\code
GPIO PIN RPi pin PWM Channel ALT FUN
12 0 0
13 1 0
18 1-12 0 5
19 1 5
40 0 0
41 1 0
45 1 0
52 0 1
53 1 1
\endcode
In order for a GPIO pin to emit output from its PWM channel, it must be set to the Alt Function given above.
Note carefully that current versions of the Raspberry Pi only expose one of these pins (GPIO 18 = RPi Pin 1-12)
on the IO headers, and therefore this is the only IO pin on the RPi that can be used for PWM.
Further it must be set to ALT FUN 5 to get PWM output.
Both PWM channels are driven by the same PWM clock, whose clock dvider can be varied using
bcm2835_pwm_set_clock(). Each channel can be separately enabled with bcm2835_pwm_set_mode().
The average output of the PWM channel is determined by the ratio of DATA/RANGE for that channel.
Use bcm2835_pwm_set_range() to set the range and bcm2835_pwm_set_data() to set the data in that ratio
Each PWM channel can run in either Balanced or Mark-Space mode. In Balanced mode, the hardware
sends a combination of clock pulses that results in an overall DATA pulses per RANGE pulses.
In Mark-Space mode, the hardware sets the output HIGH for DATA clock pulses wide, followed by
LOW for RANGE-DATA clock pulses.
The PWM clock can be set to control the PWM pulse widths. The PWM clock is derived from
a 19.2MHz clock. You can set any divider, but some common ones are provided by the BCM2835_PWM_CLOCK_DIVIDER_*
values of \ref bcm2835PWMClockDivider.
For example, say you wanted to drive a DC motor with PWM at about 1kHz,
and control the speed in 1/1024 increments from
0/1024 (stopped) through to 1024/1024 (full on). In that case you might set the
clock divider to be 16, and the RANGE to 1024. The pulse repetition frequency will be
1.2MHz/1024 = 1171.875Hz.
\par SPI
In order for bcm2835 library SPI to work, you may need to disable the SPI kernel module using:
\code
sudo raspi-config
under Advanced Options - enable Device Tree
under Advanced Options - disable SPI
Reboot.
\endcode
\par Real Time performance constraints
The bcm2835 is a library for user programs (i.e. they run in 'userland').
Such programs are not part of the kernel and are usually
subject to paging and swapping by the kernel while it does other things besides running your program.
This means that you should not expect to get real-time performance or
real-time timing constraints from such programs. In particular, there is no guarantee that the
bcm2835_delay() and bcm2835_delayMicroseconds() will return after exactly the time requested.
In fact, depending on other activity on the host, IO etc, you might get significantly longer delay times
than the one you asked for. So please dont expect to get exactly the time delay you request.
Arjan reports that you can prevent swapping on Linux with the following code fragment:
\code
struct sched_param sp;
memset(&sp, 0, sizeof(sp));
sp.sched_priority = sched_get_priority_max(SCHED_FIFO);
sched_setscheduler(0, SCHED_FIFO, &sp);
mlockall(MCL_CURRENT | MCL_FUTURE);
\endcode
\par Bindings to other languages
mikem has made Perl bindings available at CPAN:
http://search.cpan.org/~mikem/Device-BCM2835-1.9/lib/Device/BCM2835.pm
Matthew Baker has kindly made Python bindings available at:
https: github.com/mubeta06/py-libbcm2835
Gary Marks has created a Serial Peripheral Interface (SPI) command-line utility
for Raspberry Pi, based on the bcm2835 library. The
utility, spincl, is licensed under Open Source GNU GPLv3 by iP Solutions (http://ipsolutionscorp.com), as a
free download with source included: http://ipsolutionscorp.com/raspberry-pi-spi-utility/
\par Open Source Licensing GPL V2
This is the appropriate option if you want to share the source code of your
application with everyone you distribute it to, and you also want to give them
the right to share who uses it. If you wish to use this software under Open
Source Licensing, you must contribute all your source code to the open source
community in accordance with the GPL Version 2 when your application is
distributed. See http://www.gnu.org/copyleft/gpl.html and COPYING
\par Acknowledgements
Some of this code has been inspired by Dom and Gert.
The I2C code has been inspired by Alan Barr.
\par Revision History
\version 1.0 Initial release
\version 1.1 Minor bug fixes
\version 1.2 Added support for SPI
\version 1.3 Added bcm2835_spi_transfern()
\version 1.4 Fixed a problem that prevented SPI CE1 being used. Reported by David Robinson.
\version 1.5 Added bcm2835_close() to deinit the library. Suggested by C?sar Ortiz
\version 1.6 Document testing on 2012-07-15-wheezy-raspbian and Occidentalisv01
Functions bcm2835_gpio_ren(), bcm2835_gpio_fen(), bcm2835_gpio_hen()
bcm2835_gpio_len(), bcm2835_gpio_aren() and bcm2835_gpio_afen() now
changes only the pin specified. Other pins that were already previously
enabled stay enabled.
Added bcm2835_gpio_clr_ren(), bcm2835_gpio_clr_fen(), bcm2835_gpio_clr_hen()
bcm2835_gpio_clr_len(), bcm2835_gpio_clr_aren(), bcm2835_gpio_clr_afen()
to clear the enable for individual pins, suggested by Andreas Sundstrom.
\version 1.7 Added bcm2835_spi_transfernb to support different buffers for read and write.
\version 1.8 Improvements to read barrier, as suggested by maddin.
\version 1.9 Improvements contributed by mikew:
I noticed that it was mallocing memory for the mmaps on /dev/mem.
It's not necessary to do that, you can just mmap the file directly,
so I've removed the mallocs (and frees).
I've also modified delayMicroseconds() to use nanosleep() for long waits,
and a busy wait on a high resolution timer for the rest. This is because
I've found that calling nanosleep() takes at least 100-200 us.
You need to link using '-lrt' using this version.
I've added some unsigned casts to the debug prints to silence compiler
warnings I was getting, fixed some typos, and changed the value of
BCM2835_PAD_HYSTERESIS_ENABLED to 0x08 as per Gert van Loo's doc at
http://www.scribd.com/doc/101830961/GPIO-Pads-Control2
Also added a define for the passwrd value that Gert says is needed to
change pad control settings.
\version 1.10 Changed the names of the delay functions to bcm2835_delay()
and bcm2835_delayMicroseconds() to prevent collisions with wiringPi.
Macros to map delay()-> bcm2835_delay() and
Macros to map delayMicroseconds()-> bcm2835_delayMicroseconds(), which
can be disabled by defining BCM2835_NO_DELAY_COMPATIBILITY
\version 1.11 Fixed incorrect link to download file
\version 1.12 New GPIO pin definitions for RPi version 2 (which has a different GPIO mapping)
\version 1.13 New GPIO pin definitions for RPi version 2 plug P5
Hardware base pointers are now available (after initialisation) externally as bcm2835_gpio
bcm2835_pwm bcm2835_clk bcm2835_pads bcm2835_spi0.
\version 1.14 Now compiles even if CLOCK_MONOTONIC_RAW is not available, uses CLOCK_MONOTONIC instead.
Fixed errors in documentation of SPI divider frequencies based on 250MHz clock.
Reported by Ben Simpson.
\version 1.15 Added bcm2835_close() to end of examples as suggested by Mark Wolfe.
\version 1.16 Added bcm2835_gpio_set_multi, bcm2835_gpio_clr_multi and bcm2835_gpio_write_multi
to allow a mask of pins to be set all at once. Requested by Sebastian Loncar.
\version 1.17 Added bcm2835_gpio_write_mask. Requested by Sebastian Loncar.
\version 1.18 Added bcm2835_i2c_* functions. Changes to bcm2835_delayMicroseconds:
now uses the RPi system timer counter, instead of clock_gettime, for improved accuracy.
No need to link with -lrt now. Contributed by Arjan van Vught.
\version 1.19 Removed inlines added by previous patch since they don't seem to work everywhere.
Reported by olly.
\version 1.20 Patch from Mark Dootson to close /dev/mem after access to the peripherals has been granted.
\version 1.21 delayMicroseconds is now not susceptible to 32 bit timer overruns.
Patch courtesy Jeremy Mortis.
\version 1.22 Fixed incorrect definition of BCM2835_GPFEN0 which broke the ability to set
falling edge events. Reported by Mark Dootson.
\version 1.23 Added bcm2835_i2c_set_baudrate and bcm2835_i2c_read_register_rs.
Improvements to bcm2835_i2c_read and bcm2835_i2c_write functions
to fix ocasional reads not completing. Patched by Mark Dootson.
\version 1.24 Mark Dootson p[atched a problem with his previously submitted code
under high load from other processes.
\version 1.25 Updated author and distribution location details to airspayce.com
\version 1.26 Added missing unmapmem for pads in bcm2835_close to prevent a memory leak.
Reported by Hartmut Henkel.
\version 1.27 bcm2835_gpio_set_pad() no longer needs BCM2835_PAD_PASSWRD: it is
now automatically included.
Added suport for PWM mode with bcm2835_pwm_* functions.
\version 1.28 Fixed a problem where bcm2835_spi_writenb() would have problems with transfers of more than
64 bytes dues to read buffer filling. Patched by Peter Würtz.
\version 1.29 Further fix to SPI from Peter Würtz.
\version 1.30 10 microsecond delays from bcm2835_spi_transfer and bcm2835_spi_transfern for
significant performance improvements, Patch by Alan Watson.
\version 1.31 Fix a GCC warning about dummy variable, patched by Alan Watson. Thanks.
\version 1.32 Added option I2C_V1 definition to compile for version 1 RPi.
By default I2C code is generated for the V2 RPi which has SDA1 and SCL1 connected.
Contributed by Malcolm Wiles based on work by Arvi Govindaraj.
\version 1.33 Added command line utilities i2c and gpio to examples. Contributed by Shahrooz Shahparnia.
\version 1.34 Added bcm2835_i2c_write_read_rs() which writes an arbitrary number of bytes,
sends a repeat start, and reads from the device. Contributed by Eduardo Steinhorst.
\version 1.35 Fix build errors when compiled under Qt. Also performance improvements with SPI transfers. Contributed b Udo Klaas.
\version 1.36 Make automake's test runner detect that we're skipping tests when not root, the second
one makes us skip the test when using fakeroot (as used when building
Debian packages). Contributed by Guido Günther.
\version 1.37 Moved confiure.in to configure.ac as receommnded by autoreconf.<br>
Improvements to bcm2835_st_read to account for possible timer overflow, contributed by 'Ed'.<br>
Added definitions for Raspberry Pi B+ J8 header GPIO pins.<br>
\version 1.38 Added bcm2835_regbase for the benefit of C# wrappers, patch by Frank Hommers <br>
\version 1.39 Beta version of RPi2 compatibility. Not tested here on RPi2 hardware.
Testers please confirm correct operation on RPi2.<br>
Unneccessary 'volatile' qualifiers removed from all variables and signatures.<br>
Removed unsupportable PWM dividers, based on a report from Christophe Cecillon.<br>
Minor improvements to spi.c example.<br>
\version 1.40 Correct operation on RPi2 has been confirmed.<br>
Fixed a number of compiler errors and warnings that occur when bcm2835.h is included
in code compiled with -Wall -Woverflow -Wstrict-overflow -Wshadow -Wextra -pedantic.
Reported by tlhackque.<br>
Fixed a problem where calling bcm2835_delayMicroseconds loops forever when debug is set. Reported by tlhackque.<br>
Reinstated use of volatile in 2 functions where there was a danger of lost reads or writes. Reported by tlhackque.<br>
\version 1.41 Added BCM2835_VERSION macro and new function bcm2835_version(); Requested by tlhackque.<br>
Improvements to peripheral memory barriers as suggested by tlhackque.<br>
Reinstated some necessary volatile declarations as requested by tlhackque.<br>
\version 1.42 Further improvements to memory barriers with the patient assistance and patches of tlhackque.<br>
\version 1.43 Fixed problems with compiling barriers on RPI 2 with Arch Linux and gcc 4.9.2.
Reported and patched by Lars Christensen.<br>
Testing on RPI 2, with ArchLinuxARM-rpi-2-latest and 2015-02-16-raspbian-wheezy.<br>
\version 1.44 Added documention about the need for device tree to be enabled on RPI2.<br>
Improvements to detection of availablity of DMB instruction based on value of __ARM_ARCH macro.<br>
\version 1.45 Fixed an error in the pad group offsets that would prevent bcm2835_gpio_set_pad()
and bcm2835_gpio_pad() working correctly with non-0 pad groups. Reported by Guido.
\version 1.46 2015-09-18
Added symbolic definitions for remaining pins on 40 pin GPIO header on RPi 2. <br>
\version 1.47 2015-11-18
Fixed possibly incorrect reads in bcm2835_i2c_read_register_rs, patch from Eckhardt Ulrich.<br>
\version 1.48 2015-12-08
Added patch from Eckhardt Ulrich that fixed problems that could cause hanging with bcm2835_i2c_read_register_rs
and others.
\version 1.49 2016-01-05
Added patch from Jonathan Perkin with new functions bcm2835_gpio_eds_multi() and bcm2835_gpio_set_eds_multi().
\version 1.50 2016-02-28
Added support for running as non-root, permitting access to GPIO only. Functions
bcm2835_spi_begin() and bcm2835_i2c_begin() will now return 0 if not running as root
(which prevents access to the SPI and I2C peripherals, amongst others).
Testing on Raspbian Jessie.
\author Mike McCauley (mikem@airspayce.com) DO NOT CONTACT THE AUTHOR DIRECTLY: USE THE LISTS
*/
/* Defines for BCM2835 */
#ifndef BCM2835_H
#define BCM2835_H
#include <stdint.h>
#define BCM2835_VERSION 10050 /* Version 1.50 */
/* RPi 2 is ARM v7, and has DMB instruction for memory barriers.
Older RPis are ARM v6 and don't, so a coprocessor instruction must be used instead.
However, not all versions of gcc in all distros support the dmb assembler instruction even on conmpatible processors.
This test is so any ARMv7 or higher processors with suitable GCC will use DMB.
*/
#if __ARM_ARCH >= 7
#define BCM2835_HAVE_DMB
#endif
/*! \defgroup constants Constants for passing to and from library functions
The values here are designed to be passed to various functions in the bcm2835 library.
@{
*/
/*! This means pin HIGH, true, 3.3volts on a pin. */
#define HIGH 0x1
/*! This means pin LOW, false, 0volts on a pin. */
#define LOW 0x0
/*! Speed of the core clock core_clk */
#define BCM2835_CORE_CLK_HZ 250000000 /*!< 250 MHz */
/*! On RPi2 with BCM2836, and all recent OSs, the base of the peripherals is read from a /proc file */
#define BMC2835_RPI2_DT_FILENAME "/proc/device-tree/soc/ranges"
/*! Offset into BMC2835_RPI2_DT_FILENAME for the peripherals base address */
#define BMC2835_RPI2_DT_PERI_BASE_ADDRESS_OFFSET 4
/*! Offset into BMC2835_RPI2_DT_FILENAME for the peripherals size address */
#define BMC2835_RPI2_DT_PERI_SIZE_OFFSET 8
/*! Physical addresses for various peripheral register sets
Base Physical Address of the BCM 2835 peripheral registers
Note this is different for the RPi2 BCM2836, where this is derived from /proc/device-tree/soc/ranges
If /proc/device-tree/soc/ranges exists on a RPi 1 OS, it would be expected to contain the
following numbers:
*/
/*! Peripherals block base address on RPi 1 */
#define BCM2835_PERI_BASE 0x20000000
/*! Size of the peripherals block on RPi 1 */
#define BCM2835_PERI_SIZE 0x01000000
/*! Offsets for the bases of various peripherals within the peripherals block
/ Base Address of the System Timer registers
*/
#define BCM2835_ST_BASE 0x3000
/*! Base Address of the Pads registers */
#define BCM2835_GPIO_PADS 0x100000
/*! Base Address of the Clock/timer registers */
#define BCM2835_CLOCK_BASE 0x101000
/*! Base Address of the GPIO registers */
#define BCM2835_GPIO_BASE 0x200000
/*! Base Address of the SPI0 registers */
#define BCM2835_SPI0_BASE 0x204000
/*! Base Address of the BSC0 registers */
#define BCM2835_BSC0_BASE 0x205000
/*! Base Address of the PWM registers */
#define BCM2835_GPIO_PWM 0x20C000
/*! Base Address of the BSC1 registers */
#define BCM2835_BSC1_BASE 0x804000
/*! Physical address and size of the peripherals block
May be overridden on RPi2
*/
extern uint32_t *bcm2835_peripherals_base;
/*! Size of the peripherals block to be mapped */
extern uint32_t bcm2835_peripherals_size;
/*! Virtual memory address of the mapped peripherals block */
extern uint32_t *bcm2835_peripherals;
/*! Base of the ST (System Timer) registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_st;
/*! Base of the GPIO registers.
Available after bcm2835_init has been called
*/
extern volatile uint32_t *bcm2835_gpio;
/*! Base of the PWM registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_pwm;
/*! Base of the CLK registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_clk;
/*! Base of the PADS registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_pads;
/*! Base of the SPI0 registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_spi0;
/*! Base of the BSC0 registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_bsc0;
/*! Base of the BSC1 registers.
Available after bcm2835_init has been called (as root)
*/
extern volatile uint32_t *bcm2835_bsc1;
/*! \brief bcm2835RegisterBase
Register bases for bcm2835_regbase()
*/
typedef enum
{
BCM2835_REGBASE_ST = 1, /*!< Base of the ST (System Timer) registers. */
BCM2835_REGBASE_GPIO = 2, /*!< Base of the GPIO registers. */
BCM2835_REGBASE_PWM = 3, /*!< Base of the PWM registers. */
BCM2835_REGBASE_CLK = 4, /*!< Base of the CLK registers. */
BCM2835_REGBASE_PADS = 5, /*!< Base of the PADS registers. */
BCM2835_REGBASE_SPI0 = 6, /*!< Base of the SPI0 registers. */
BCM2835_REGBASE_BSC0 = 7, /*!< Base of the BSC0 registers. */
BCM2835_REGBASE_BSC1 = 8 /*!< Base of the BSC1 registers. */
} bcm2835RegisterBase;
/*! Size of memory page on RPi */
#define BCM2835_PAGE_SIZE (4*1024)
/*! Size of memory block on RPi */
#define BCM2835_BLOCK_SIZE (4*1024)
/* Defines for GPIO
The BCM2835 has 54 GPIO pins.
BCM2835 data sheet, Page 90 onwards.
*/
/*! GPIO register offsets from BCM2835_GPIO_BASE.
Offsets into the GPIO Peripheral block in bytes per 6.1 Register View
*/
#define BCM2835_GPFSEL0 0x0000 /*!< GPIO Function Select 0 */
#define BCM2835_GPFSEL1 0x0004 /*!< GPIO Function Select 1 */
#define BCM2835_GPFSEL2 0x0008 /*!< GPIO Function Select 2 */
#define BCM2835_GPFSEL3 0x000c /*!< GPIO Function Select 3 */
#define BCM2835_GPFSEL4 0x0010 /*!< GPIO Function Select 4 */
#define BCM2835_GPFSEL5 0x0014 /*!< GPIO Function Select 5 */
#define BCM2835_GPSET0 0x001c /*!< GPIO Pin Output Set 0 */
#define BCM2835_GPSET1 0x0020 /*!< GPIO Pin Output Set 1 */
#define BCM2835_GPCLR0 0x0028 /*!< GPIO Pin Output Clear 0 */
#define BCM2835_GPCLR1 0x002c /*!< GPIO Pin Output Clear 1 */
#define BCM2835_GPLEV0 0x0034 /*!< GPIO Pin Level 0 */
#define BCM2835_GPLEV1 0x0038 /*!< GPIO Pin Level 1 */
#define BCM2835_GPEDS0 0x0040 /*!< GPIO Pin Event Detect Status 0 */
#define BCM2835_GPEDS1 0x0044 /*!< GPIO Pin Event Detect Status 1 */
#define BCM2835_GPREN0 0x004c /*!< GPIO Pin Rising Edge Detect Enable 0 */
#define BCM2835_GPREN1 0x0050 /*!< GPIO Pin Rising Edge Detect Enable 1 */
#define BCM2835_GPFEN0 0x0058 /*!< GPIO Pin Falling Edge Detect Enable 0 */
#define BCM2835_GPFEN1 0x005c /*!< GPIO Pin Falling Edge Detect Enable 1 */
#define BCM2835_GPHEN0 0x0064 /*!< GPIO Pin High Detect Enable 0 */
#define BCM2835_GPHEN1 0x0068 /*!< GPIO Pin High Detect Enable 1 */
#define BCM2835_GPLEN0 0x0070 /*!< GPIO Pin Low Detect Enable 0 */
#define BCM2835_GPLEN1 0x0074 /*!< GPIO Pin Low Detect Enable 1 */
#define BCM2835_GPAREN0 0x007c /*!< GPIO Pin Async. Rising Edge Detect 0 */
#define BCM2835_GPAREN1 0x0080 /*!< GPIO Pin Async. Rising Edge Detect 1 */
#define BCM2835_GPAFEN0 0x0088 /*!< GPIO Pin Async. Falling Edge Detect 0 */
#define BCM2835_GPAFEN1 0x008c /*!< GPIO Pin Async. Falling Edge Detect 1 */
#define BCM2835_GPPUD 0x0094 /*!< GPIO Pin Pull-up/down Enable */
#define BCM2835_GPPUDCLK0 0x0098 /*!< GPIO Pin Pull-up/down Enable Clock 0 */
#define BCM2835_GPPUDCLK1 0x009c /*!< GPIO Pin Pull-up/down Enable Clock 1 */
/*! \brief bcm2835PortFunction
Port function select modes for bcm2835_gpio_fsel()
*/
typedef enum
{
BCM2835_GPIO_FSEL_INPT = 0x00, /*!< Input 0b000 */
BCM2835_GPIO_FSEL_OUTP = 0x01, /*!< Output 0b001 */
BCM2835_GPIO_FSEL_ALT0 = 0x04, /*!< Alternate function 0 0b100 */
BCM2835_GPIO_FSEL_ALT1 = 0x05, /*!< Alternate function 1 0b101 */
BCM2835_GPIO_FSEL_ALT2 = 0x06, /*!< Alternate function 2 0b110, */
BCM2835_GPIO_FSEL_ALT3 = 0x07, /*!< Alternate function 3 0b111 */
BCM2835_GPIO_FSEL_ALT4 = 0x03, /*!< Alternate function 4 0b011 */
BCM2835_GPIO_FSEL_ALT5 = 0x02, /*!< Alternate function 5 0b010 */
BCM2835_GPIO_FSEL_MASK = 0x07 /*!< Function select bits mask 0b111 */
} bcm2835FunctionSelect;
/*! \brief bcm2835PUDControl
Pullup/Pulldown defines for bcm2835_gpio_pud()
*/
typedef enum
{
BCM2835_GPIO_PUD_OFF = 0x00, /*!< Off ? disable pull-up/down 0b00 */
BCM2835_GPIO_PUD_DOWN = 0x01, /*!< Enable Pull Down control 0b01 */
BCM2835_GPIO_PUD_UP = 0x02 /*!< Enable Pull Up control 0b10 */
} bcm2835PUDControl;
/*! Pad control register offsets from BCM2835_GPIO_PADS */
#define BCM2835_PADS_GPIO_0_27 0x002c /*!< Pad control register for pads 0 to 27 */
#define BCM2835_PADS_GPIO_28_45 0x0030 /*!< Pad control register for pads 28 to 45 */
#define BCM2835_PADS_GPIO_46_53 0x0034 /*!< Pad control register for pads 46 to 53 */
/*! Pad Control masks */
#define BCM2835_PAD_PASSWRD (0x5A << 24) /*!< Password to enable setting pad mask */
#define BCM2835_PAD_SLEW_RATE_UNLIMITED 0x10 /*!< Slew rate unlimited */
#define BCM2835_PAD_HYSTERESIS_ENABLED 0x08 /*!< Hysteresis enabled */
#define BCM2835_PAD_DRIVE_2mA 0x00 /*!< 2mA drive current */
#define BCM2835_PAD_DRIVE_4mA 0x01 /*!< 4mA drive current */
#define BCM2835_PAD_DRIVE_6mA 0x02 /*!< 6mA drive current */
#define BCM2835_PAD_DRIVE_8mA 0x03 /*!< 8mA drive current */
#define BCM2835_PAD_DRIVE_10mA 0x04 /*!< 10mA drive current */
#define BCM2835_PAD_DRIVE_12mA 0x05 /*!< 12mA drive current */
#define BCM2835_PAD_DRIVE_14mA 0x06 /*!< 14mA drive current */
#define BCM2835_PAD_DRIVE_16mA 0x07 /*!< 16mA drive current */
/*! \brief bcm2835PadGroup
Pad group specification for bcm2835_gpio_pad()
*/
typedef enum
{
BCM2835_PAD_GROUP_GPIO_0_27 = 0, /*!< Pad group for GPIO pads 0 to 27 */
BCM2835_PAD_GROUP_GPIO_28_45 = 1, /*!< Pad group for GPIO pads 28 to 45 */
BCM2835_PAD_GROUP_GPIO_46_53 = 2 /*!< Pad group for GPIO pads 46 to 53 */
} bcm2835PadGroup;
/*! \brief GPIO Pin Numbers
Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying BCM GPIO pin numbers.
These can be passed as a pin number to any function requiring a pin.
Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins
and some can adopt an alternate function.
RPi version 2 has some slightly different pinouts, and these are values RPI_V2_*.
RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*.
At bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively
When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI
and cant be controlled independently.
If you are using the RPi Compute Module, just use the GPIO number: there is no need to use one of these
symbolic names
*/
typedef enum
{
RPI_GPIO_P1_03 = 0, /*!< Version 1, Pin P1-03 */
RPI_GPIO_P1_05 = 1, /*!< Version 1, Pin P1-05 */
RPI_GPIO_P1_07 = 4, /*!< Version 1, Pin P1-07 */
RPI_GPIO_P1_08 = 14, /*!< Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD */
RPI_GPIO_P1_10 = 15, /*!< Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD */
RPI_GPIO_P1_11 = 17, /*!< Version 1, Pin P1-11 */
RPI_GPIO_P1_12 = 18, /*!< Version 1, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */
RPI_GPIO_P1_13 = 21, /*!< Version 1, Pin P1-13 */
RPI_GPIO_P1_15 = 22, /*!< Version 1, Pin P1-15 */
RPI_GPIO_P1_16 = 23, /*!< Version 1, Pin P1-16 */
RPI_GPIO_P1_18 = 24, /*!< Version 1, Pin P1-18 */
RPI_GPIO_P1_19 = 10, /*!< Version 1, Pin P1-19, MOSI when SPI0 in use */
RPI_GPIO_P1_21 = 9, /*!< Version 1, Pin P1-21, MISO when SPI0 in use */
RPI_GPIO_P1_22 = 25, /*!< Version 1, Pin P1-22 */
RPI_GPIO_P1_23 = 11, /*!< Version 1, Pin P1-23, CLK when SPI0 in use */
RPI_GPIO_P1_24 = 8, /*!< Version 1, Pin P1-24, CE0 when SPI0 in use */
RPI_GPIO_P1_26 = 7, /*!< Version 1, Pin P1-26, CE1 when SPI0 in use */
/* RPi Version 2 */
RPI_V2_GPIO_P1_03 = 2, /*!< Version 2, Pin P1-03 */
RPI_V2_GPIO_P1_05 = 3, /*!< Version 2, Pin P1-05 */
RPI_V2_GPIO_P1_07 = 4, /*!< Version 2, Pin P1-07 */
RPI_V2_GPIO_P1_08 = 14, /*!< Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD */
RPI_V2_GPIO_P1_10 = 15, /*!< Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD */
RPI_V2_GPIO_P1_11 = 17, /*!< Version 2, Pin P1-11 */
RPI_V2_GPIO_P1_12 = 18, /*!< Version 2, Pin P1-12, can be PWM channel 0 in ALT FUN 5 */
RPI_V2_GPIO_P1_13 = 27, /*!< Version 2, Pin P1-13 */
RPI_V2_GPIO_P1_15 = 22, /*!< Version 2, Pin P1-15 */
RPI_V2_GPIO_P1_16 = 23, /*!< Version 2, Pin P1-16 */
RPI_V2_GPIO_P1_18 = 24, /*!< Version 2, Pin P1-18 */
RPI_V2_GPIO_P1_19 = 10, /*!< Version 2, Pin P1-19, MOSI when SPI0 in use */
RPI_V2_GPIO_P1_21 = 9, /*!< Version 2, Pin P1-21, MISO when SPI0 in use */
RPI_V2_GPIO_P1_22 = 25, /*!< Version 2, Pin P1-22 */
RPI_V2_GPIO_P1_23 = 11, /*!< Version 2, Pin P1-23, CLK when SPI0 in use */
RPI_V2_GPIO_P1_24 = 8, /*!< Version 2, Pin P1-24, CE0 when SPI0 in use */
RPI_V2_GPIO_P1_26 = 7, /*!< Version 2, Pin P1-26, CE1 when SPI0 in use */
RPI_V2_GPIO_P1_29 = 5, /*!< Version 2, Pin P1-29 */
RPI_V2_GPIO_P1_31 = 6, /*!< Version 2, Pin P1-31 */
RPI_V2_GPIO_P1_32 = 12, /*!< Version 2, Pin P1-32 */
RPI_V2_GPIO_P1_33 = 13, /*!< Version 2, Pin P1-33 */
RPI_V2_GPIO_P1_35 = 19, /*!< Version 2, Pin P1-35 */
RPI_V2_GPIO_P1_36 = 16, /*!< Version 2, Pin P1-36 */
RPI_V2_GPIO_P1_37 = 26, /*!< Version 2, Pin P1-37 */
RPI_V2_GPIO_P1_38 = 20, /*!< Version 2, Pin P1-38 */
RPI_V2_GPIO_P1_40 = 21, /*!< Version 2, Pin P1-40 */
/* RPi Version 2, new plug P5 */
RPI_V2_GPIO_P5_03 = 28, /*!< Version 2, Pin P5-03 */
RPI_V2_GPIO_P5_04 = 29, /*!< Version 2, Pin P5-04 */
RPI_V2_GPIO_P5_05 = 30, /*!< Version 2, Pin P5-05 */
RPI_V2_GPIO_P5_06 = 31, /*!< Version 2, Pin P5-06 */
/* RPi B+ J8 header, also RPi 2 40 pin GPIO header */
RPI_BPLUS_GPIO_J8_03 = 2, /*!< B+, Pin J8-03 */
RPI_BPLUS_GPIO_J8_05 = 3, /*!< B+, Pin J8-05 */
RPI_BPLUS_GPIO_J8_07 = 4, /*!< B+, Pin J8-07 */
RPI_BPLUS_GPIO_J8_08 = 14, /*!< B+, Pin J8-08, defaults to alt function 0 UART0_TXD */
RPI_BPLUS_GPIO_J8_10 = 15, /*!< B+, Pin J8-10, defaults to alt function 0 UART0_RXD */
RPI_BPLUS_GPIO_J8_11 = 17, /*!< B+, Pin J8-11 */
RPI_BPLUS_GPIO_J8_12 = 18, /*!< B+, Pin J8-12, can be PWM channel 0 in ALT FUN 5 */
RPI_BPLUS_GPIO_J8_13 = 27, /*!< B+, Pin J8-13 */
RPI_BPLUS_GPIO_J8_15 = 22, /*!< B+, Pin J8-15 */
RPI_BPLUS_GPIO_J8_16 = 23, /*!< B+, Pin J8-16 */
RPI_BPLUS_GPIO_J8_18 = 24, /*!< B+, Pin J8-18 */
RPI_BPLUS_GPIO_J8_19 = 10, /*!< B+, Pin J8-19, MOSI when SPI0 in use */
RPI_BPLUS_GPIO_J8_21 = 9, /*!< B+, Pin J8-21, MISO when SPI0 in use */
RPI_BPLUS_GPIO_J8_22 = 25, /*!< B+, Pin J8-22 */
RPI_BPLUS_GPIO_J8_23 = 11, /*!< B+, Pin J8-23, CLK when SPI0 in use */
RPI_BPLUS_GPIO_J8_24 = 8, /*!< B+, Pin J8-24, CE0 when SPI0 in use */
RPI_BPLUS_GPIO_J8_26 = 7, /*!< B+, Pin J8-26, CE1 when SPI0 in use */
RPI_BPLUS_GPIO_J8_29 = 5, /*!< B+, Pin J8-29, */
RPI_BPLUS_GPIO_J8_31 = 6, /*!< B+, Pin J8-31, */
RPI_BPLUS_GPIO_J8_32 = 12, /*!< B+, Pin J8-32, */
RPI_BPLUS_GPIO_J8_33 = 13, /*!< B+, Pin J8-33, */
RPI_BPLUS_GPIO_J8_35 = 19, /*!< B+, Pin J8-35, */
RPI_BPLUS_GPIO_J8_36 = 16, /*!< B+, Pin J8-36, */
RPI_BPLUS_GPIO_J8_37 = 26, /*!< B+, Pin J8-37, */
RPI_BPLUS_GPIO_J8_38 = 20, /*!< B+, Pin J8-38, */
RPI_BPLUS_GPIO_J8_40 = 21 /*!< B+, Pin J8-40, */
} RPiGPIOPin;
/* Defines for SPI
GPIO register offsets from BCM2835_SPI0_BASE.
Offsets into the SPI Peripheral block in bytes per 10.5 SPI Register Map
*/
#define BCM2835_SPI0_CS 0x0000 /*!< SPI Master Control and Status */
#define BCM2835_SPI0_FIFO 0x0004 /*!< SPI Master TX and RX FIFOs */
#define BCM2835_SPI0_CLK 0x0008 /*!< SPI Master Clock Divider */
#define BCM2835_SPI0_DLEN 0x000c /*!< SPI Master Data Length */
#define BCM2835_SPI0_LTOH 0x0010 /*!< SPI LOSSI mode TOH */
#define BCM2835_SPI0_DC 0x0014 /*!< SPI DMA DREQ Controls */
/* Register masks for SPI0_CS */
#define BCM2835_SPI0_CS_LEN_LONG 0x02000000 /*!< Enable Long data word in Lossi mode if DMA_LEN is set */
#define BCM2835_SPI0_CS_DMA_LEN 0x01000000 /*!< Enable DMA mode in Lossi mode */
#define BCM2835_SPI0_CS_CSPOL2 0x00800000 /*!< Chip Select 2 Polarity */
#define BCM2835_SPI0_CS_CSPOL1 0x00400000 /*!< Chip Select 1 Polarity */
#define BCM2835_SPI0_CS_CSPOL0 0x00200000 /*!< Chip Select 0 Polarity */
#define BCM2835_SPI0_CS_RXF 0x00100000 /*!< RXF - RX FIFO Full */
#define BCM2835_SPI0_CS_RXR 0x00080000 /*!< RXR RX FIFO needs Reading (full) */
#define BCM2835_SPI0_CS_TXD 0x00040000 /*!< TXD TX FIFO can accept Data */
#define BCM2835_SPI0_CS_RXD 0x00020000 /*!< RXD RX FIFO contains Data */
#define BCM2835_SPI0_CS_DONE 0x00010000 /*!< Done transfer Done */
#define BCM2835_SPI0_CS_TE_EN 0x00008000 /*!< Unused */
#define BCM2835_SPI0_CS_LMONO 0x00004000 /*!< Unused */
#define BCM2835_SPI0_CS_LEN 0x00002000 /*!< LEN LoSSI enable */
#define BCM2835_SPI0_CS_REN 0x00001000 /*!< REN Read Enable */
#define BCM2835_SPI0_CS_ADCS 0x00000800 /*!< ADCS Automatically Deassert Chip Select */
#define BCM2835_SPI0_CS_INTR 0x00000400 /*!< INTR Interrupt on RXR */
#define BCM2835_SPI0_CS_INTD 0x00000200 /*!< INTD Interrupt on Done */
#define BCM2835_SPI0_CS_DMAEN 0x00000100 /*!< DMAEN DMA Enable */
#define BCM2835_SPI0_CS_TA 0x00000080 /*!< Transfer Active */
#define BCM2835_SPI0_CS_CSPOL 0x00000040 /*!< Chip Select Polarity */
#define BCM2835_SPI0_CS_CLEAR 0x00000030 /*!< Clear FIFO Clear RX and TX */
#define BCM2835_SPI0_CS_CLEAR_RX 0x00000020 /*!< Clear FIFO Clear RX */
#define BCM2835_SPI0_CS_CLEAR_TX 0x00000010 /*!< Clear FIFO Clear TX */
#define BCM2835_SPI0_CS_CPOL 0x00000008 /*!< Clock Polarity */
#define BCM2835_SPI0_CS_CPHA 0x00000004 /*!< Clock Phase */
#define BCM2835_SPI0_CS_CS 0x00000003 /*!< Chip Select */
/*! \brief bcm2835SPIBitOrder SPI Bit order
Specifies the SPI data bit ordering for bcm2835_spi_setBitOrder()
*/
typedef enum
{
BCM2835_SPI_BIT_ORDER_LSBFIRST = 0, /*!< LSB First */
BCM2835_SPI_BIT_ORDER_MSBFIRST = 1 /*!< MSB First */
}bcm2835SPIBitOrder;
/*! \brief SPI Data mode
Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
*/
typedef enum
{
BCM2835_SPI_MODE0 = 0, /*!< CPOL = 0, CPHA = 0 */
BCM2835_SPI_MODE1 = 1, /*!< CPOL = 0, CPHA = 1 */
BCM2835_SPI_MODE2 = 2, /*!< CPOL = 1, CPHA = 0 */
BCM2835_SPI_MODE3 = 3 /*!< CPOL = 1, CPHA = 1 */
}bcm2835SPIMode;
/*! \brief bcm2835SPIChipSelect
Specify the SPI chip select pin(s)
*/
typedef enum
{
BCM2835_SPI_CS0 = 0, /*!< Chip Select 0 */
BCM2835_SPI_CS1 = 1, /*!< Chip Select 1 */
BCM2835_SPI_CS2 = 2, /*!< Chip Select 2 (ie pins CS1 and CS2 are asserted) */
BCM2835_SPI_CS_NONE = 3 /*!< No CS, control it yourself */
} bcm2835SPIChipSelect;
/*! \brief bcm2835SPIClockDivider
Specifies the divider used to generate the SPI clock from the system clock.
Figures below give the divider, clock period and clock frequency.
Clock divided is based on nominal base clock rate of 250MHz
It is reported that (contrary to the documentation) any even divider may used.
The frequencies shown for each divider have been confirmed by measurement.
*/
typedef enum
{
BCM2835_SPI_CLOCK_DIVIDER_65536 = 0, /*!< 65536 = 262.144us = 3.814697260kHz */
BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768, /*!< 32768 = 131.072us = 7.629394531kHz */
BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384, /*!< 16384 = 65.536us = 15.25878906kHz */
BCM2835_SPI_CLOCK_DIVIDER_8192 = 8192, /*!< 8192 = 32.768us = 30/51757813kHz */
BCM2835_SPI_CLOCK_DIVIDER_4096 = 4096, /*!< 4096 = 16.384us = 61.03515625kHz */
BCM2835_SPI_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 8.192us = 122.0703125kHz */
BCM2835_SPI_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 4.096us = 244.140625kHz */
BCM2835_SPI_CLOCK_DIVIDER_512 = 512, /*!< 512 = 2.048us = 488.28125kHz */
BCM2835_SPI_CLOCK_DIVIDER_256 = 256, /*!< 256 = 1.024us = 976.5625kHz */
BCM2835_SPI_CLOCK_DIVIDER_128 = 128, /*!< 128 = 512ns = = 1.953125MHz */
BCM2835_SPI_CLOCK_DIVIDER_64 = 64, /*!< 64 = 256ns = 3.90625MHz */
BCM2835_SPI_CLOCK_DIVIDER_32 = 32, /*!< 32 = 128ns = 7.8125MHz */
BCM2835_SPI_CLOCK_DIVIDER_16 = 16, /*!< 16 = 64ns = 15.625MHz */
BCM2835_SPI_CLOCK_DIVIDER_8 = 8, /*!< 8 = 32ns = 31.25MHz */
BCM2835_SPI_CLOCK_DIVIDER_4 = 4, /*!< 4 = 16ns = 62.5MHz */
BCM2835_SPI_CLOCK_DIVIDER_2 = 2, /*!< 2 = 8ns = 125MHz, fastest you can get */
BCM2835_SPI_CLOCK_DIVIDER_1 = 1 /*!< 1 = 262.144us = 3.814697260kHz, same as 0/65536 */
} bcm2835SPIClockDivider;
/* Defines for I2C
GPIO register offsets from BCM2835_BSC*_BASE.
Offsets into the BSC Peripheral block in bytes per 3.1 BSC Register Map
*/
#define BCM2835_BSC_C 0x0000 /*!< BSC Master Control */
#define BCM2835_BSC_S 0x0004 /*!< BSC Master Status */
#define BCM2835_BSC_DLEN 0x0008 /*!< BSC Master Data Length */
#define BCM2835_BSC_A 0x000c /*!< BSC Master Slave Address */
#define BCM2835_BSC_FIFO 0x0010 /*!< BSC Master Data FIFO */
#define BCM2835_BSC_DIV 0x0014 /*!< BSC Master Clock Divider */
#define BCM2835_BSC_DEL 0x0018 /*!< BSC Master Data Delay */
#define BCM2835_BSC_CLKT 0x001c /*!< BSC Master Clock Stretch Timeout */
/* Register masks for BSC_C */
#define BCM2835_BSC_C_I2CEN 0x00008000 /*!< I2C Enable, 0 = disabled, 1 = enabled */
#define BCM2835_BSC_C_INTR 0x00000400 /*!< Interrupt on RX */
#define BCM2835_BSC_C_INTT 0x00000200 /*!< Interrupt on TX */
#define BCM2835_BSC_C_INTD 0x00000100 /*!< Interrupt on DONE */
#define BCM2835_BSC_C_ST 0x00000080 /*!< Start transfer, 1 = Start a new transfer */
#define BCM2835_BSC_C_CLEAR_1 0x00000020 /*!< Clear FIFO Clear */
#define BCM2835_BSC_C_CLEAR_2 0x00000010 /*!< Clear FIFO Clear */
#define BCM2835_BSC_C_READ 0x00000001 /*!< Read transfer */
/* Register masks for BSC_S */
#define BCM2835_BSC_S_CLKT 0x00000200 /*!< Clock stretch timeout */
#define BCM2835_BSC_S_ERR 0x00000100 /*!< ACK error */
#define BCM2835_BSC_S_RXF 0x00000080 /*!< RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BCM2835_BSC_S_TXE 0x00000040 /*!< TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full */
#define BCM2835_BSC_S_RXD 0x00000020 /*!< RXD FIFO contains data */
#define BCM2835_BSC_S_TXD 0x00000010 /*!< TXD FIFO can accept data */
#define BCM2835_BSC_S_RXR 0x00000008 /*!< RXR FIFO needs reading (full) */
#define BCM2835_BSC_S_TXW 0x00000004 /*!< TXW FIFO needs writing (full) */
#define BCM2835_BSC_S_DONE 0x00000002 /*!< Transfer DONE */
#define BCM2835_BSC_S_TA 0x00000001 /*!< Transfer Active */
#define BCM2835_BSC_FIFO_SIZE 16 /*!< BSC FIFO size */
/*! \brief bcm2835I2CClockDivider
Specifies the divider used to generate the I2C clock from the system clock.
Clock divided is based on nominal base clock rate of 250MHz
*/
typedef enum
{
BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500, /*!< 2500 = 10us = 100 kHz */
BCM2835_I2C_CLOCK_DIVIDER_626 = 626, /*!< 622 = 2.504us = 399.3610 kHz */
BCM2835_I2C_CLOCK_DIVIDER_150 = 150, /*!< 150 = 60ns = 1.666 MHz (default at reset) */
BCM2835_I2C_CLOCK_DIVIDER_148 = 148 /*!< 148 = 59ns = 1.689 MHz */
} bcm2835I2CClockDivider;
/*! \brief bcm2835I2CReasonCodes
Specifies the reason codes for the bcm2835_i2c_write and bcm2835_i2c_read functions.
*/
typedef enum
{
BCM2835_I2C_REASON_OK = 0x00, /*!< Success */
BCM2835_I2C_REASON_ERROR_NACK = 0x01, /*!< Received a NACK */
BCM2835_I2C_REASON_ERROR_CLKT = 0x02, /*!< Received Clock Stretch Timeout */
BCM2835_I2C_REASON_ERROR_DATA = 0x04 /*!< Not all data is sent / received */
} bcm2835I2CReasonCodes;
/* Defines for ST
GPIO register offsets from BCM2835_ST_BASE.
Offsets into the ST Peripheral block in bytes per 12.1 System Timer Registers
The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter.
BCM2835_ST_CLO is the System Timer Counter Lower bits register.
The system timer free-running counter lower register is a read-only register that returns the current value
of the lower 32-bits of the free running counter.
BCM2835_ST_CHI is the System Timer Counter Upper bits register.
The system timer free-running counter upper register is a read-only register that returns the current value
of the upper 32-bits of the free running counter.
*/
#define BCM2835_ST_CS 0x0000 /*!< System Timer Control/Status */
#define BCM2835_ST_CLO 0x0004 /*!< System Timer Counter Lower 32 bits */
#define BCM2835_ST_CHI 0x0008 /*!< System Timer Counter Upper 32 bits */
/*! @} */
/* Defines for PWM, word offsets (ie 4 byte multiples) */
#define BCM2835_PWM_CONTROL 0
#define BCM2835_PWM_STATUS 1
#define BCM2835_PWM_DMAC 2
#define BCM2835_PWM0_RANGE 4
#define BCM2835_PWM0_DATA 5
#define BCM2835_PWM_FIF1 6
#define BCM2835_PWM1_RANGE 8
#define BCM2835_PWM1_DATA 9
/* Defines for PWM Clock, word offsets (ie 4 byte multiples) */
#define BCM2835_PWMCLK_CNTL 40
#define BCM2835_PWMCLK_DIV 41
#define BCM2835_PWM_PASSWRD (0x5A << 24) /*!< Password to enable setting PWM clock */
#define BCM2835_PWM1_MS_MODE 0x8000 /*!< Run in Mark/Space mode */
#define BCM2835_PWM1_USEFIFO 0x2000 /*!< Data from FIFO */
#define BCM2835_PWM1_REVPOLAR 0x1000 /*!< Reverse polarity */
#define BCM2835_PWM1_OFFSTATE 0x0800 /*!< Ouput Off state */
#define BCM2835_PWM1_REPEATFF 0x0400 /*!< Repeat last value if FIFO empty */
#define BCM2835_PWM1_SERIAL 0x0200 /*!< Run in serial mode */
#define BCM2835_PWM1_ENABLE 0x0100 /*!< Channel Enable */
#define BCM2835_PWM0_MS_MODE 0x0080 /*!< Run in Mark/Space mode */
#define BCM2835_PWM_CLEAR_FIFO 0x0040 /*!< Clear FIFO */
#define BCM2835_PWM0_USEFIFO 0x0020 /*!< Data from FIFO */
#define BCM2835_PWM0_REVPOLAR 0x0010 /*!< Reverse polarity */
#define BCM2835_PWM0_OFFSTATE 0x0008 /*!< Ouput Off state */
#define BCM2835_PWM0_REPEATFF 0x0004 /*!< Repeat last value if FIFO empty */
#define BCM2835_PWM0_SERIAL 0x0002 /*!< Run in serial mode */
#define BCM2835_PWM0_ENABLE 0x0001 /*!< Channel Enable */
/*! \brief bcm2835PWMClockDivider
Specifies the divider used to generate the PWM clock from the system clock.
Figures below give the divider, clock period and clock frequency.
Clock divided is based on nominal PWM base clock rate of 19.2MHz
The frequencies shown for each divider have been confirmed by measurement
*/
typedef enum
{
BCM2835_PWM_CLOCK_DIVIDER_2048 = 2048, /*!< 2048 = 9.375kHz */
BCM2835_PWM_CLOCK_DIVIDER_1024 = 1024, /*!< 1024 = 18.75kHz */
BCM2835_PWM_CLOCK_DIVIDER_512 = 512, /*!< 512 = 37.5kHz */
BCM2835_PWM_CLOCK_DIVIDER_256 = 256, /*!< 256 = 75kHz */