{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"cvfpu","owner":"openhwgroup","isFork":false,"description":"Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":6,"issueCount":35,"starsCount":382,"forksCount":104,"license":"Apache License 2.0","participation":[0,4,0,0,2,0,3,0,4,0,1,1,3,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T13:45:50.948Z"}},{"type":"Public","name":"cv32e40p","owner":"openhwgroup","isFork":false,"description":"CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform","allTopics":["riscv","riscv32imfc"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":11,"issueCount":32,"starsCount":889,"forksCount":388,"license":"Other","participation":[5,12,19,2,3,9,2,2,11,10,15,16,15,9,8,2,8,16,7,6,3,9,10,7,14,5,7,3,8,0,8,2,2,3,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-05T08:38:16.168Z"}},{"type":"Public","name":"cv-hpdcache","owner":"openhwgroup","isFork":false,"description":"RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":2,"starsCount":36,"forksCount":12,"license":"Other","participation":[0,5,8,8,1,0,0,0,0,0,0,4,3,1,3,3,0,7,2,1,1,0,0,0,1,1,1,2,0,0,0,1,5,2,0,5,6,4,11,2,1,0,1,2,1,11,0,0,0,0,3,4],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-06-04T09:37:31.894Z"}},{"type":"Public","name":"cve2","owner":"openhwgroup","isFork":true,"description":"The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":10,"issueCount":170,"starsCount":23,"forksCount":485,"license":"Apache License 2.0","participation":[0,0,1,1,1,0,2,8,1,8,3,4,1,8,0,5,1,1,0,0,0,0,3,0,0,0,2,0,1,0,0,0,0,1,0,0,0,2,0,0,0,0,0,0,0,0,0,0,0,0,2,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-28T18:23:18.740Z"}},{"type":"Public","name":"core-v-xif","owner":"openhwgroup","isFork":false,"description":"RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":16,"starsCount":53,"forksCount":23,"license":"Other","participation":[0,0,2,1,0,0,0,0,0,0,0,1,0,0,7,1,0,0,1,2,5,2,9,11,1,3,2,1,0,0,2,4,24,7,25,3,2,13,5,3,7,5,0,0,3,0,0,0,0,0,2,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-22T09:42:14.058Z"}},{"type":"Public","name":"core-v-mcu-uvm","owner":"openhwgroup","isFork":false,"description":"CORE-V MCU UVM Environment and Test Bench","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":16,"starsCount":13,"forksCount":6,"license":null,"participation":[0,0,0,0,1,0,1,0,1,1,0,0,0,0,0,3,0,0,0,0,0,0,0,0,0,0,8,2,2,0,1,1,3,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-17T12:21:27.644Z"}},{"type":"Public","name":"cva5","owner":"openhwgroup","isFork":false,"description":"The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":10,"starsCount":52,"forksCount":14,"license":"Apache License 2.0","participation":[0,3,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,0,1,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-03T02:37:02.525Z"}},{"type":"Public","name":"core-v-mcu","owner":"openhwgroup","isFork":false,"description":"This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.","allTopics":["microcontroller","riscv","systemverilog","openhwgroup"],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":5,"issueCount":73,"starsCount":158,"forksCount":51,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-18T19:04:43.646Z"}},{"type":"Public","name":"cv32e40s","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, secure RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":123,"forksCount":22,"license":"Other","participation":[9,10,6,12,18,3,1,6,16,25,8,30,42,57,57,16,14,24,16,4,2,0,0,8,5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-12-06T18:08:01.876Z"}},{"type":"Public","name":"cv32e40x","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, compute RISC-V core based on the CV32E40P","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":3,"issueCount":28,"starsCount":194,"forksCount":48,"license":"Other","participation":[4,6,4,4,11,3,1,5,13,21,8,22,31,35,27,12,14,13,12,2,0,0,0,5,3,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-12-01T12:00:39.410Z"}},{"type":"Public archive","name":"cv32e41p","owner":"openhwgroup","isFork":false,"description":"4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":2,"issueCount":9,"starsCount":26,"forksCount":11,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-08-16T21:27:36.015Z"}},{"type":"Public","name":"cva5-accelerators","owner":"openhwgroup","isFork":false,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":0,"starsCount":0,"forksCount":4,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-02T20:55:13.065Z"}},{"type":"Public","name":"advanced-riscv-verification-methodologies","owner":"openhwgroup","isFork":false,"description":"Advanced Verification Methodologies for RISC-V and related IP","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":7,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-01-16T20:18:44.876Z"}},{"type":"Public","name":"timer_unit","owner":"openhwgroup","isFork":true,"description":"","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":1,"forksCount":4,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2021-02-18T03:50:50.237Z"}},{"type":"Public","name":"apb_interrupt_cntrl","owner":"openhwgroup","isFork":true,"description":"Small and simple APB interrupt controller","allTopics":[],"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":0,"starsCount":3,"forksCount":7,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-09T17:25:12.174Z"}}],"repositoryCount":15,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}