{"payload":{"pageCount":1,"repositories":[{"type":"Public","name":"dromajo","owner":"chipsalliance","isFork":false,"description":"RISC-V RV64GC emulator designed for RTL co-simulation","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":2,"issueCount":18,"starsCount":201,"forksCount":59,"license":"Apache License 2.0","participation":[0,0,0,0,0,1,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,4,3,0,0,0,0,0,0,0,0,0,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-25T04:56:27.547Z"}},{"type":"Public","name":"verilator","owner":"chipsalliance","isFork":true,"description":"Verilator open-source SystemVerilog simulator and lint system","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":0,"starsCount":33,"forksCount":542,"license":"GNU Lesser General Public License v3.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-24T11:31:30.103Z"}},{"type":"Public","name":"Surelog","owner":"chipsalliance","isFork":false,"description":"SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX ","topicNames":["parser","linter","preprocessor","antlr","verilog","python-api","systemverilog","uvm","elaboration","vpi"],"topicsNotShown":4,"allTopics":["parser","linter","preprocessor","antlr","verilog","python-api","systemverilog","uvm","elaboration","vpi","antlr4-grammar","parser-ast","vpi-api","vpi-standard"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":49,"starsCount":333,"forksCount":66,"license":"Apache License 2.0","participation":[28,15,17,22,11,13,17,23,20,14,15,2,16,30,23,13,29,36,14,12,21,10,9,18,8,0,4,5,19,12,4,0,15,8,0,0,2,0,2,0,0,0,0,0,0,0,0,0,0,1,7,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-15T03:53:51.680Z"}},{"type":"Public","name":"UHDM","owner":"chipsalliance","isFork":false,"description":"Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX","topicNames":["vpi-api","serialization","listener","systemverilog","ieee-standard","vpi-interface"],"topicsNotShown":0,"allTopics":["vpi-api","serialization","listener","systemverilog","ieee-standard","vpi-interface"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":14,"starsCount":184,"forksCount":37,"license":"Apache License 2.0","participation":[13,13,13,20,7,5,14,8,9,9,2,3,5,22,6,7,12,20,8,6,6,2,6,7,2,0,0,4,20,6,0,0,4,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-15T02:41:08.451Z"}},{"type":"Public","name":"verible","owner":"chipsalliance","isFork":false,"description":"Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server","topicNames":["productivity","analysis","style-linter","language-server-protocol","syntax-tree","lexer","yacc","systemverilog","hacktoberfest","lsp-server"],"topicsNotShown":7,"allTopics":["productivity","analysis","style-linter","language-server-protocol","syntax-tree","lexer","yacc","systemverilog","hacktoberfest","lsp-server","systemverilog-parser","systemverilog-developer","sv-lrm","verible","parser","formatter","linter"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":33,"issueCount":453,"starsCount":1222,"forksCount":191,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-12T12:33:26.183Z"}},{"type":"Public","name":"VeeR-ISS","owner":"chipsalliance","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":4,"issueCount":11,"starsCount":105,"forksCount":30,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-06T14:19:02.477Z"}},{"type":"Public","name":"tree-sitter-firrtl","owner":"chipsalliance","isFork":false,"description":"FIRRTL grammar for tree-sitter","topicNames":["tree-sitter","parser","firrtl"],"topicsNotShown":0,"allTopics":["tree-sitter","parser","firrtl"],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":3,"starsCount":8,"forksCount":7,"license":"Apache License 2.0","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-20T12:28:25.912Z"}},{"type":"Public","name":"systemc-compiler","owner":"chipsalliance","isFork":false,"description":"Intel Compiler for SystemC","topicNames":[],"topicsNotShown":0,"allTopics":[],"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":0,"starsCount":18,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-06-01T16:24:54.198Z"}}],"repositoryCount":8,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}