{"payload":{"pageCount":2,"repositories":[{"type":"Public","name":"oss-cad-suite-build","owner":"YosysHQ","isFork":false,"description":"Multi-platform nightly builds of open source digital design and verification tools","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":2,"issueCount":41,"starsCount":687,"forksCount":65,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-15T11:32:47.703Z"}},{"type":"Public","name":"nextpnr","owner":"YosysHQ","isFork":false,"description":"nextpnr portable FPGA place and route tool","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":12,"issueCount":102,"starsCount":1216,"forksCount":233,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-15T09:43:07.692Z"}},{"type":"Public","name":"yosys","owner":"YosysHQ","isFork":false,"description":"Yosys Open SYnthesis Suite","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":89,"issueCount":388,"starsCount":3201,"forksCount":841,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-14T15:22:25.860Z"}},{"type":"Public","name":"sby","owner":"YosysHQ","isFork":false,"description":"SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":12,"issueCount":33,"starsCount":370,"forksCount":73,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-14T01:07:42.907Z"}},{"type":"Public","name":"furo-ys","owner":"YosysHQ","isFork":true,"description":"A clean customizable documentation theme for Sphinx","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Sass","color":"#a53b70"},"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":294,"license":"MIT License","participation":[5,0,0,0,0,1,3,0,3,0,4,1,0,14,2,3,9,0,0,0,0,1,0,0,0,1,1,0,0,1,0,1,0,0,0,0,25,1,0,4,0,0,0,0,0,1,3,0,1,9,22,16],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-14T01:07:19.368Z"}},{"type":"Public","name":"abc","owner":"YosysHQ","isFork":true,"description":"ABC: System for Sequential Logic Synthesis and Formal Verification","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C","color":"#555555"},"pullRequestCount":1,"issueCount":0,"starsCount":24,"forksCount":509,"license":"Other","participation":[6,0,2,1,0,3,1,3,9,11,3,2,10,3,9,14,13,16,4,4,0,1,8,1,2,3,16,5,0,3,1,3,0,0,9,5,1,7,6,3,6,26,1,14,9,4,0,22,3,1,0,0],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-10T19:42:47.857Z"}},{"type":"Public","name":"riscv-formal","owner":"YosysHQ","isFork":false,"description":"RISC-V Formal Verification Framework","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":2,"issueCount":3,"starsCount":87,"forksCount":20,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-09T05:40:44.752Z"}},{"type":"Public","name":"eqy","owner":"YosysHQ","isFork":false,"description":"Equivalence checking with Yosys","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":10,"starsCount":27,"forksCount":5,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-09T05:39:29.294Z"}},{"type":"Public","name":"mcy","owner":"YosysHQ","isFork":false,"description":"Mutation Cover with Yosys (MCY)","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":1,"starsCount":74,"forksCount":9,"license":"ISC License","participation":[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,0,1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,2,0,1,0,2],"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-08T11:45:44.198Z"}},{"type":"Public","name":"apicula","owner":"YosysHQ","isFork":false,"description":"Project Apicula 🐝: bitstream documentation for Gowin FPGAs","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":2,"issueCount":11,"starsCount":426,"forksCount":62,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-05-03T10:28:24.219Z"}},{"type":"Public","name":"icestorm","owner":"YosysHQ","isFork":false,"description":"Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":16,"issueCount":35,"starsCount":952,"forksCount":220,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-21T22:22:59.974Z"}},{"type":"Public","name":"mau","owner":"YosysHQ","isFork":false,"description":"Modular Application Utilities","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":2,"issueCount":1,"starsCount":3,"forksCount":2,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-04-19T00:10:54.377Z"}},{"type":"Public","name":"picorv32","owner":"YosysHQ","isFork":false,"description":"PicoRV32 - A Size-Optimized RISC-V CPU","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":11,"issueCount":54,"starsCount":2794,"forksCount":705,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-26T18:19:50.565Z"}},{"type":"Public","name":"VlogHammer","owner":"YosysHQ","isFork":false,"description":"A Verilog Synthesis Regression Test","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Shell","color":"#89e051"},"pullRequestCount":2,"issueCount":0,"starsCount":33,"forksCount":8,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-21T12:11:32.580Z"}},{"type":"Public","name":"setup-oss-cad-suite","owner":"YosysHQ","isFork":false,"description":"Set up your GitHub Actions workflow with a OSS CAD Suite","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"TypeScript","color":"#3178c6"},"pullRequestCount":0,"issueCount":3,"starsCount":13,"forksCount":2,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-21T12:10:02.281Z"}},{"type":"Public","name":"sby-gui","owner":"YosysHQ","isFork":false,"description":"GUI for SymbiYosys","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":0,"issueCount":7,"starsCount":12,"forksCount":4,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-03-21T12:01:25.222Z"}},{"type":"Public","name":"prjtrellis","owner":"YosysHQ","isFork":false,"description":"Documenting the Lattice ECP5 bit-stream format.","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":12,"issueCount":31,"starsCount":382,"forksCount":86,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-29T14:43:47.460Z"}},{"type":"Public","name":"scy","owner":"YosysHQ","isFork":false,"description":"Sequence of Covers with Yosys","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":0,"issueCount":1,"starsCount":5,"forksCount":1,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2024-01-29T08:09:59.004Z"}},{"type":"Public","name":"prjtrellis-db","owner":"YosysHQ","isFork":false,"description":"Project Trellis database","topicNames":[],"topicsNotShown":0,"primaryLanguage":null,"pullRequestCount":1,"issueCount":0,"starsCount":11,"forksCount":11,"license":"Creative Commons Zero v1.0 Universal","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-10-04T13:10:35.059Z"}},{"type":"Public","name":"nextpnr-tests","owner":"YosysHQ","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":0,"starsCount":4,"forksCount":4,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-17T23:59:43.226Z"}},{"type":"Public","name":"padring","owner":"YosysHQ","isFork":false,"description":"A padring generator for ASICs","topicNames":["asic","eda","chip","vlsi","yosys"],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":2,"starsCount":22,"forksCount":10,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-05-17T15:44:06.174Z"}},{"type":"Public","name":"nerv","owner":"YosysHQ","isFork":false,"description":"Naive Educational RISC V processor","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"SystemVerilog","color":"#DAE1C2"},"pullRequestCount":1,"issueCount":1,"starsCount":67,"forksCount":12,"license":"Other","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-04-26T22:29:56.191Z"}},{"type":"Public","name":".github","owner":"YosysHQ","isFork":false,"description":"","topicNames":[],"topicsNotShown":0,"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":0,"forksCount":0,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2023-04-04T09:41:57.886Z"}},{"type":"Public","name":"yosyshq.github.io","owner":"YosysHQ","isFork":false,"description":"www.yosyshq.net","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":0,"starsCount":4,"forksCount":1,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-12-05T16:21:39.924Z"}},{"type":"Public","name":"yosys-web","owner":"YosysHQ","isFork":false,"description":"Yosys Web Page","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"HTML","color":"#e34c26"},"pullRequestCount":0,"issueCount":1,"starsCount":3,"forksCount":6,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-12-05T16:21:10.625Z"}},{"type":"Public","name":"yosys-tests","owner":"YosysHQ","isFork":false,"description":"Collection of test cases for Yosys","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":1,"issueCount":1,"starsCount":17,"forksCount":7,"license":null,"participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2022-01-04T16:41:49.335Z"}},{"type":"Public","name":"pyosys-tests","owner":"YosysHQ","isFork":false,"description":"pyosys tests","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Python","color":"#3572A5"},"pullRequestCount":0,"issueCount":1,"starsCount":4,"forksCount":2,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-11-27T08:56:42.805Z"}},{"type":"Public","name":"Sublime-Yosys","owner":"YosysHQ","isFork":false,"description":"Yosys syntax highlighter for the Sublime Text 3 editor","topicNames":[],"topicsNotShown":0,"primaryLanguage":null,"pullRequestCount":0,"issueCount":0,"starsCount":5,"forksCount":0,"license":"BSD Zero Clause License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-04-16T14:56:45.677Z"}},{"type":"Public","name":"yosys-bench","owner":"YosysHQ","isFork":false,"description":"Benchmarks for Yosys development","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"Verilog","color":"#b2b7f8"},"pullRequestCount":4,"issueCount":0,"starsCount":19,"forksCount":6,"license":"ISC License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2020-02-17T16:27:30.968Z"}},{"type":"Public","name":"arachne-pnr","owner":"YosysHQ","isFork":false,"description":"Place and route tool for FPGAs","topicNames":[],"topicsNotShown":0,"primaryLanguage":{"name":"C++","color":"#f34b7d"},"pullRequestCount":1,"issueCount":23,"starsCount":412,"forksCount":73,"license":"MIT License","participation":null,"lastUpdated":{"hasBeenPushedTo":true,"timestamp":"2019-07-28T22:12:46.012Z"}}],"repositoryCount":35,"userInfo":null,"searchable":true,"definitions":[],"typeFilters":[{"id":"all","text":"All"},{"id":"public","text":"Public"},{"id":"source","text":"Sources"},{"id":"fork","text":"Forks"},{"id":"archived","text":"Archived"},{"id":"mirror","text":"Mirrors"},{"id":"template","text":"Templates"}],"compactMode":false},"title":"Repositories"}