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<section id="nep-38-using-simd-optimization-instructions-for-performance">
<span id="nep38"></span><h1>NEP 38 — Using SIMD optimization instructions for performance<a class="headerlink" href="#nep-38-using-simd-optimization-instructions-for-performance" title="Link to this heading">#</a></h1>
<dl class="field-list simple">
<dt class="field-odd">Author<span class="colon">:</span></dt>
<dd class="field-odd"><p>Sayed Adel, Matti Picus, Ralf Gommers</p>
</dd>
<dt class="field-even">Status<span class="colon">:</span></dt>
<dd class="field-even"><p>Final</p>
</dd>
<dt class="field-odd">Type<span class="colon">:</span></dt>
<dd class="field-odd"><p>Standards</p>
</dd>
<dt class="field-even">Created<span class="colon">:</span></dt>
<dd class="field-even"><p>2019-11-25</p>
</dd>
<dt class="field-odd">Resolution<span class="colon">:</span></dt>
<dd class="field-odd"><p><a class="reference external" href="https://mail.python.org/archives/list/numpy-discussion@python.org/thread/PVWJ74UVBRZ5ZWF6MDU7EUSJXVNILAQB/#PVWJ74UVBRZ5ZWF6MDU7EUSJXVNILAQB">https://mail.python.org/archives/list/numpy-discussion@python.org/thread/PVWJ74UVBRZ5ZWF6MDU7EUSJXVNILAQB/#PVWJ74UVBRZ5ZWF6MDU7EUSJXVNILAQB</a></p>
</dd>
</dl>
<section id="abstract">
<h2>Abstract<a class="headerlink" href="#abstract" title="Link to this heading">#</a></h2>
<p>While compilers are getting better at using hardware-specific routines to
optimize code, they sometimes do not produce optimal results. Also, we would
like to be able to copy binary optimized C-extension modules from one machine
to another with the same base architecture (x86, ARM, or PowerPC) but with
different capabilities without recompiling.</p>
<p>We have a mechanism in the ufunc machinery to <a class="reference external" href="https://github.com/numpy/numpy/blob/v1.17.4/numpy/core/code_generators/generate_umath.py#L50">build alternative loops</a>
indexed by CPU feature name. At import (in <code class="docutils literal notranslate"><span class="pre">InitOperators</span></code>), the loop
function that matches the run-time CPU info <a class="reference external" href="https://github.com/numpy/numpy/blob/v1.17.4/numpy/core/code_generators/generate_umath.py#L1038">is chosen</a> from the candidates.This
NEP proposes a mechanism to build on that for many more features and
architectures. The steps proposed are to:</p>
<ul class="simple">
<li><p>Establish a set of well-defined, architecture-agnostic, universal intrinsics
which capture features available across architectures.</p></li>
<li><p>Capture these universal intrinsics in a set of C macros and use the macros
to build code paths for sets of features from the baseline up to the maximum
set of features available on that architecture. Offer these as a limited
number of compiled alternative code paths.</p></li>
<li><p>At runtime, discover which CPU features are available, and choose from among
the possible code paths accordingly.</p></li>
</ul>
</section>
<section id="motivation-and-scope">
<h2>Motivation and scope<a class="headerlink" href="#motivation-and-scope" title="Link to this heading">#</a></h2>
<p>Traditionally NumPy has depended on compilers to generate optimal code
specifically for the target architecture.
However few users today compile NumPy locally for their machines. Most use the
binary packages which must provide run-time support for the lowest-common
denominator CPU architecture. Thus NumPy cannot take advantage of
more advanced features of their CPU processors, since they may not be available
on all users’ systems.</p>
<p>Traditionally, CPU features have been exposed through <a class="reference external" href="https://software.intel.com/en-us/cpp-compiler-developer-guide-and-reference-intrinsics">intrinsics</a> which are
compiler-specific instructions that map directly to assembly instructions.
Recently there were discussions about the effectiveness of adding more
intrinsics (e.g., <a class="reference external" href="https://github.com/numpy/numpy/pull/11113">gh-11113</a> for AVX optimizations for floats). In the past,
architecture-specific code was added to NumPy for <a class="reference external" href="https://github.com/numpy/numpy/pulls?q=is%3Apr+avx512+is%3Aclosed">fast avx512 routines</a> in
various ufuncs, using the mechanism described above to choose the best loop
for the architecture. However the code is not generic and does not generalize
to other architectures.</p>
<p>Recently, OpenCV moved to using <a class="reference external" href="https://docs.opencv.org/master/df/d91/group__core__hal__intrin.html">universal intrinsics</a> in the Hardware
Abstraction Layer (HAL) which provided a nice abstraction for common shared
Single Instruction Multiple Data (SIMD) constructs. This NEP proposes a similar
mechanism for NumPy. There are three stages to using the mechanism:</p>
<ul class="simple">
<li><p>Infrastructure is provided in the code for abstract intrinsics. The ufunc
machinery will be extended using sets of these abstract intrinsics, so that
a single ufunc will be expressed as a set of loops, going from a minimal to
a maximal set of possibly available intrinsics.</p></li>
<li><p>At compile time, compiler macros and CPU detection are used to turn the
abstract intrinsics into concrete intrinsic calls. Any intrinsics not
available on the platform, either because the CPU does not support them
(and so cannot be tested) or because the abstract intrinsic does not have a
parallel concrete intrinsic on the platform will not error, rather the
corresponding loop will not be produced and added to the set of
possibilities.</p></li>
<li><p>At runtime, the CPU detection code will further limit the set of loops
available, and the optimal one will be chosen for the ufunc.</p></li>
</ul>
<p>The current NEP proposes only to use the runtime feature detection and optimal
loop selection mechanism for ufuncs. Future NEPS may propose other uses for the
proposed solution.</p>
<p>The ufunc machinery already has the ability to select an optimal loop for
specifically available CPU features at runtime, currently used for <code class="docutils literal notranslate"><span class="pre">avx2</span></code>,
<code class="docutils literal notranslate"><span class="pre">fma</span></code> and <code class="docutils literal notranslate"><span class="pre">avx512f</span></code> loops (in the generated <code class="docutils literal notranslate"><span class="pre">__umath_generated.c</span></code> file);
universal intrinsics would extend the generated code to include more loop
variants.</p>
</section>
<section id="usage-and-impact">
<h2>Usage and impact<a class="headerlink" href="#usage-and-impact" title="Link to this heading">#</a></h2>
<p>The end user will be able to get a list of intrinsics available for their
platform and compiler. Optionally,
the user may be able to specify which of the loops available at runtime will be
used, perhaps via an environment variable to enable benchmarking the impact of
the different loops. There should be no direct impact to naive end users, the
results of all the loops should be identical to within a small number (1-3?)
ULPs. On the other hand, users with more powerful machines should notice a
significant performance boost.</p>
<section id="binary-releases-wheels-on-pypi-and-conda-packages">
<h3>Binary releases - wheels on PyPI and conda packages<a class="headerlink" href="#binary-releases-wheels-on-pypi-and-conda-packages" title="Link to this heading">#</a></h3>
<p>The binaries released by this process will be larger since they include all
possible loops for the architecture. Some packagers may prefer to limit the
number of loops in order to limit the size of the binaries, we would hope they
would still support a wide range of families of architectures. Note this
problem already exists in the Intel MKL offering, where the binary package
includes an extensive set of alternative shared objects (DLLs) for various CPU
alternatives.</p>
</section>
<section id="source-builds">
<h3>Source builds<a class="headerlink" href="#source-builds" title="Link to this heading">#</a></h3>
<p>See “Detailed Description” below. A source build where the packager knows
details of the target machine could theoretically produce a smaller binary by
choosing to compile only the loops needed by the target via command line
arguments.</p>
</section>
<section id="how-to-run-benchmarks-to-assess-performance-benefits">
<h3>How to run benchmarks to assess performance benefits<a class="headerlink" href="#how-to-run-benchmarks-to-assess-performance-benefits" title="Link to this heading">#</a></h3>
<p>Adding more code which use intrinsics will make the code harder to maintain.
Therefore, such code should only be added if it yields a significant
performance benefit. Assessing this performance benefit can be nontrivial.
To aid with this, the implementation for this NEP will add a way to select
which instruction sets can be used at <em>runtime</em> via environment variables.
(name TBD). This ability is critical for CI code verification.</p>
</section>
<section id="diagnostics">
<h3>Diagnostics<a class="headerlink" href="#diagnostics" title="Link to this heading">#</a></h3>
<p>A new dictionary <code class="docutils literal notranslate"><span class="pre">__cpu_features__</span></code> will be available to python. The keys are
the available features, the value is a boolean whether the feature is available
or not. Various new private
C functions will be used internally to query available features. These
might be exposed via specific c-extension modules for testing.</p>
</section>
<section id="workflow-for-adding-a-new-cpu-architecture-specific-optimization">
<h3>Workflow for adding a new CPU architecture-specific optimization<a class="headerlink" href="#workflow-for-adding-a-new-cpu-architecture-specific-optimization" title="Link to this heading">#</a></h3>
<p>NumPy will always have a baseline C implementation for any code that may be
a candidate for SIMD vectorization. If a contributor wants to add SIMD
support for some architecture (typically the one of most interest to them),
this comment is the beginning of a tutorial on how to do so:
<a class="github reference external" href="https://github.com/numpy/numpy/pull/13516#issuecomment-558859638">numpy/numpy#13516</a></p>
<p id="tradeoffs">As of this moment, NumPy has a number of <code class="docutils literal notranslate"><span class="pre">avx512f</span></code> and <code class="docutils literal notranslate"><span class="pre">avx2</span></code> and <code class="docutils literal notranslate"><span class="pre">fma</span></code>
SIMD loops for many ufuncs. These would likely be the first candidates
to be ported to universal intrinsics. The expectation is that the new
implementation may cause a regression in benchmarks, but not increase the
size of the binary. If the regression is not minimal, we may choose to keep
the X86-specific code for that platform and use the universal intrinsic code
for other platforms.</p>
<p>Any new PRs to implement ufuncs using intrinsics will be expected to use the
universal intrinsics. If it can be demonstrated that the use of universal
intrinsics is too awkward or is not performant enough, platform specific code
may be accepted as well. In rare cases, a single-platform only PR may be
accepted, but it would have to be examined within the framework of preferring
a solution using universal intrinsics.</p>
<p>The subjective criteria for accepting new loops are:</p>
<ul class="simple">
<li><p>correctness: the new code must not decrease accuracy by more than 1-3 ULPs
even at edge points in the algorithm.</p></li>
<li><p>code bloat: both source code size and especially binary size of the compiled
wheel.</p></li>
<li><p>maintainability: how readable is the code</p></li>
<li><p>performance: benchmarks must show a significant performance boost</p></li>
</ul>
<section id="adding-a-new-intrinsic">
<span id="new-intrinsics"></span><h4>Adding a new intrinsic<a class="headerlink" href="#adding-a-new-intrinsic" title="Link to this heading">#</a></h4>
<p>If a contributor wants to use a platform-specific SIMD instruction that is not
yet supported as a universal intrinsic, then:</p>
<ol class="arabic simple">
<li><p>It should be added as a universal intrinsic for all platforms</p></li>
<li><p>If it does not have an equivalent instruction on other platforms (e.g.
<code class="docutils literal notranslate"><span class="pre">_mm512_mask_i32gather_ps</span></code> in <code class="docutils literal notranslate"><span class="pre">AVX512</span></code>), then no universal intrinsic
should be added and a platform-specific <code class="docutils literal notranslate"><span class="pre">ufunc</span></code> or a short helper function
should be written instead. If such a helper function is used, it must be
wrapped with the feature macros, and a reasonable non-intrinsic fallback to
be used by default.</p></li>
</ol>
<p>We expect (2) to be the exception. The contributor and maintainers should
consider whether that single-platform intrinsic is worth it compared to using
the best available universal intrinsic based implementation.</p>
</section>
</section>
<section id="reuse-by-other-projects">
<h3>Reuse by other projects<a class="headerlink" href="#reuse-by-other-projects" title="Link to this heading">#</a></h3>
<p>It would be nice if the universal intrinsics would be available to other
libraries like SciPy or Astropy that also build ufuncs, but that is not an
explicit goal of the first implementation of this NEP.</p>
</section>
</section>
<section id="backward-compatibility">
<h2>Backward compatibility<a class="headerlink" href="#backward-compatibility" title="Link to this heading">#</a></h2>
<p>There should be no impact on backwards compatibility.</p>
</section>
<section id="detailed-description">
<h2>Detailed description<a class="headerlink" href="#detailed-description" title="Link to this heading">#</a></h2>
<p>The CPU-specific are mapped to universal intrinsics which are
similar for all x86 SIMD variants, ARM SIMD variants etc. For example, the
NumPy universal intrinsic <code class="docutils literal notranslate"><span class="pre">npyv_load_u32</span></code> maps to:</p>
<ul class="simple">
<li><p><code class="docutils literal notranslate"><span class="pre">vld1q_u32</span></code> for ARM based NEON</p></li>
<li><p><code class="docutils literal notranslate"><span class="pre">_mm256_loadu_si256</span></code> for x86 based AVX2</p></li>
<li><p><code class="docutils literal notranslate"><span class="pre">_mm512_loadu_si512</span></code> for x86 based AVX-512</p></li>
</ul>
<p>Anyone writing a SIMD loop will use the <code class="docutils literal notranslate"><span class="pre">npyv_load_u32</span></code> macro instead of the
architecture specific intrinsic. The code also supplies guard macros for
compilation and runtime, so that the proper loops can be chosen.</p>
<p>Two new build options are available to <code class="docutils literal notranslate"><span class="pre">runtests.py</span></code> and <code class="docutils literal notranslate"><span class="pre">setup.py</span></code>:
<code class="docutils literal notranslate"><span class="pre">--cpu-baseline</span></code> and <code class="docutils literal notranslate"><span class="pre">--cpu-dispatch</span></code>.
The absolute minimum required features to compile are defined by
<code class="docutils literal notranslate"><span class="pre">--cpu-baseline</span></code>. For instance, on <code class="docutils literal notranslate"><span class="pre">x86_64</span></code> this defaults to <code class="docutils literal notranslate"><span class="pre">SSE3</span></code>. The
minimum features will be enabled if the compiler support it. The
set of additional intrinsics that can be detected and used as sets of
requirements to dispatch on are set by <code class="docutils literal notranslate"><span class="pre">--cpu-dispatch</span></code>. For instance, on
<code class="docutils literal notranslate"><span class="pre">x86_64</span></code> this defaults to <code class="docutils literal notranslate"><span class="pre">[SSSE3,</span> <span class="pre">SSE41,</span> <span class="pre">POPCNT,</span> <span class="pre">SSE42,</span> <span class="pre">AVX,</span> <span class="pre">F16C,</span> <span class="pre">XOP,</span>
<span class="pre">FMA4,</span> <span class="pre">FMA3,</span> <span class="pre">AVX2,</span> <span class="pre">AVX512F,</span> <span class="pre">AVX512CD,</span> <span class="pre">AVX512_KNL,</span> <span class="pre">AVX512_KNM,</span> <span class="pre">AVX512_SKX,</span>
<span class="pre">AVX512_CLX,</span> <span class="pre">AVX512_CNL,</span> <span class="pre">AVX512_ICL]</span></code>. These features are all mapped to a
c-level boolean array <code class="docutils literal notranslate"><span class="pre">npy__cpu_have</span></code>, and a c-level convenience function
<code class="docutils literal notranslate"><span class="pre">npy_cpu_have(int</span> <span class="pre">feature_id)</span></code> queries this array, and the results are stored
in <code class="docutils literal notranslate"><span class="pre">__cpu_features__</span></code> at runtime.</p>
<p>When importing the ufuncs, the available compiled loops’ required features are
matched to the ones discovered. The loop with the best match is marked to be
called by the ufunc.</p>
</section>
<section id="related-work">
<h2>Related work<a class="headerlink" href="#related-work" title="Link to this heading">#</a></h2>
<ul class="simple">
<li><p><a class="reference external" href="https://gitlab.freedesktop.org/pixman">Pixman</a> is the library used by Cairo and X to manipulate pixels. It uses
a technique like the one described here to fill a structure with function
pointers at runtime. These functions are similar to ufunc loops.</p></li>
<li><p><a class="reference external" href="http://eigen.tuxfamily.org/index.php?title=Main_Page">Eigen</a> is a C++ template library for linear algebra: matrices, vectors,
numerical solvers, and related algorithms. It is a higher level-abstraction
than the intrinsics discussed here.</p></li>
<li><p><a class="reference external" href="https://xsimd.readthedocs.io/en/latest/">xsimd</a> is a header-only C++ library for x86 and ARM that implements the
mathematical functions used in the algorithms of <code class="docutils literal notranslate"><span class="pre">boost.SIMD</span></code>.</p></li>
<li><p><a class="reference external" href="https://github.com/ermig1979/Simd">Simd</a> is a high-level image processing and machine learning library with
optimizations for different platforms.</p></li>
<li><p>OpenCV used to have the one-implementation-per-architecture design, but more
recently moved to a design that is quite similar to what is proposed in this
NEP. The top-level <a class="reference external" href="https://github.com/opencv/opencv/blob/4.1.2/modules/core/src/arithm.dispatch.cpp">dispatch code</a> includes a <a class="reference external" href="https://github.com/opencv/opencv/blob/4.1.2/modules/core/src/arithm.simd.hpp">generic header</a> that is
<a class="reference external" href="https://github.com/opencv/opencv/blob/4.1.2/modules/core/CMakeLists.txt#L3-#L13">specialized at compile time</a> by the CMakefile system.</p></li>
<li><p><a class="reference external" href="https://www.libvolk.org/doxygen/index.html">VOLK</a> is a GPL3 library used by gnuradio and others to abstract SIMD
intrinsics. They offer a set of high-level operations which have been
optimized for each architecture.</p></li>
<li><p>The C++ Standards Committee has proposed <a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p0214r8.pdf">class templates</a> for portable
SIMD programming via vector types, and <a class="reference external" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2019/n4808.pdf">namespaces</a> for the templates.</p></li>
</ul>
</section>
<section id="implementation">
<h2>Implementation<a class="headerlink" href="#implementation" title="Link to this heading">#</a></h2>
<p>Current PRs:</p>
<ul class="simple">
<li><p><a class="reference external" href="https://github.com/numpy/numpy/pull/13421">gh-13421 improve runtime detection of CPU features</a></p></li>
<li><p><a class="reference external" href="https://github.com/numpy/numpy/pull/13516">gh-13516: enable multi-platform SIMD compiler optimizations</a></p></li>
</ul>
<p>The compile-time and runtime code infrastructure are supplied by the first PR.
The second adds a demonstration of use of the infrastructure for a loop. Once
the NEP is approved, more work is needed to write loops using the mechanisms
provided by the NEP.</p>
</section>
<section id="alternatives">
<h2>Alternatives<a class="headerlink" href="#alternatives" title="Link to this heading">#</a></h2>
<p>A proposed alternative in <a class="reference external" href="https://github.com/numpy/numpy/pull/13516">gh-13516</a> is to implement loops for each CPU
architecture separately by hand, without trying to abstract common patterns in
the SIMD intrinsics (e.g., have <cite>loops.avx512.c.src</cite>, <cite>loops.avx2.c.src</cite>,
<cite>loops.sse.c.src</cite>, <cite>loops.vsx.c.src</cite>, <cite>loops.neon.c.src</cite>, etc.). This is more
similar to what PIXMAX does. There’s a lot of duplication here though, and the
manual code duplication requires a champion who will be dedicated to
implementing and maintaining that platform’s loop code.</p>
</section>
<section id="discussion">
<h2>Discussion<a class="headerlink" href="#discussion" title="Link to this heading">#</a></h2>
<p>Most of the discussion took place on the PR <a class="reference external" href="https://github.com/numpy/numpy/pull/15228">gh-15228</a> to accept this NEP.
Discussion on the mailing list mentioned <a class="reference external" href="https://www.libvolk.org/doxygen/index.html">VOLK</a> which was added to
the section on related work. The question of maintainability also was raised
both on the mailing list and in <a class="reference external" href="https://github.com/numpy/numpy/pull/15228">gh-15228</a> and resolved as follows:</p>
<ul class="simple">
<li><p>If contributors want to leverage a specific SIMD instruction, will they be
expected to add software implementation of this instruction for all other
architectures too? (see the <a class="reference internal" href="#new-intrinsics">new-intrinsics</a> part of the workflow).</p></li>
<li><p>On whom does the burden lie to verify the code and benchmarks for all
architectures? What happens if adding a universal ufunc in place of
architecture-specific code helps one architecture but harms performance
on another? (answered in the <a class="reference internal" href="#tradeoffs">tradeoffs</a> part of the workflow).</p></li>
</ul>
</section>
<section id="references-and-footnotes">
<h2>References and footnotes<a class="headerlink" href="#references-and-footnotes" title="Link to this heading">#</a></h2>
<aside class="footnote-list brackets">
<aside class="footnote brackets" id="id1" role="doc-footnote">
<span class="label"><span class="fn-bracket">[</span><a role="doc-backlink" href="#id2">1</a><span class="fn-bracket">]</span></span>
<p>Each NEP must either be explicitly labeled as placed in the public domain (see
this NEP as an example) or licensed under the <a class="reference external" href="https://www.opencontent.org/openpub/">Open Publication License</a>.</p>
</aside>
</aside>
</section>
<section id="copyright">
<h2>Copyright<a class="headerlink" href="#copyright" title="Link to this heading">#</a></h2>
<p>This document has been placed in the public domain. <a class="footnote-reference brackets" href="#id1" id="id2" role="doc-noteref"><span class="fn-bracket">[</span>1<span class="fn-bracket">]</span></a></p>
</section>
</section>
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