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channel.c
3911 lines (3339 loc) · 136 KB
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channel.c
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/* CHANNEL.C (c) Copyright Roger Bowler, 1999-2012 */
/* (c) Copyright Jan Jaeger, 1999-2012 */
/* ESA/390 Channel Emulator */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2012 */
/*-------------------------------------------------------------------*/
/* This module contains the channel subsystem functions for the */
/* Hercules S/370 and ESA/390 emulator. */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Additional credits: */
/* Measurement block support by Jan Jaeger */
/* Fix program check on NOP due to addressing - Jan Jaeger */
/* Fix program check on TIC as first ccw on RSCH - Jan Jaeger */
/* Fix PCI intermediate status flags - Jan Jaeger */
/* 64-bit IDAW support - Roger Bowler v209 @IWZ*/
/* Incorrect-length-indication-suppression - Jan Jaeger */
/* Read backward support contributed by Hackules 13jun2002 */
/* Read backward fixes contributed by Jay Jaeger 16sep2003 */
/* MIDAW support - Roger Bowler 03aug2005 @MW*/
/*-------------------------------------------------------------------*/
#include "hstdinc.h"
#define _CHANNEL_C_
#define _HENGINE_DLL_
#include "hercules.h"
#include "devtype.h"
#include "opcode.h"
#if defined(OPTION_FISHIO)
#include "w32chan.h"
#endif // defined(OPTION_FISHIO)
#if !defined(PREFETCH_STRUCT)
#define PREFETCH_STRUCT
/* Define 256 entries in the prefetch table */
#define PF_SIZE 256
/* IDAW Types */
enum PF_IDATYPE {
PF_NO_IDAW = 0,
PF_IDAW1 = 1,
PF_IDAW2 = 2,
PF_MIDAW = 3
};
typedef struct /* Prefetch data structure */
{
u_int seq; /* Counter */
u_int pos; /* Highest valid position */
u_int reqcount; /* Requested count */
U8 prevcode; /* Previous CCW opcode */
U8 opcode; /* CCW opcode */
U16 reserved;
BYTE chanstat[PF_SIZE]; /* Channel status */
U32 ccwaddr[PF_SIZE]; /* CCW address (SCSW CCW) */
U32 datalen[PF_SIZE]; /* Count (length) */
RADR dataaddr[PF_SIZE]; /* Address */
U8 ccwflags[PF_SIZE]; /* CCW flags */
U16 ccwcount[PF_SIZE]; /* Count (length) */
U32 idawaddr[PF_SIZE]; /* IDAW address */
U8 idawtype[PF_SIZE]; /* IDAW type */
U8 idawflag[PF_SIZE]; /* IDAW flags */
} PREFETCH;
#endif
void call_execute_ccw_chain(int arch_mode, void* pDevBlk);
#ifdef OPTION_IODELAY_KLUDGE
#define IODELAY(_dev) \
do { \
if (sysblk.iodelay > 0 && (_dev)->devchar[10] == 0x20) \
usleep(sysblk.iodelay); \
} while (0)
#else
#define IODELAY(_dev)
#endif
#undef CHADDRCHK
#if defined(FEATURE_ADDRESS_LIMIT_CHECKING)
#define CHADDRCHK(_addr,_dev) \
( ((_addr) > (_dev)->mainlim) \
|| ((dev->orb.flag5 & ORB5_A) \
&& ((((_dev)->pmcw.flag5 & PMCW5_LM_LOW) \
&& ((_addr) < sysblk.addrlimval)) \
|| (((_dev)->pmcw.flag5 & PMCW5_LM_HIGH) \
&& ((_addr) >= sysblk.addrlimval)) ) ))
#else /*!defined(FEATURE_ADDRESS_LIMIT_CHECKING)*/
#define CHADDRCHK(_addr,_dev) \
((_addr) > (_dev)->mainlim)
#endif /*!defined(FEATURE_ADDRESS_LIMIT_CHECKING)*/
#if !defined(_CHANNEL_C)
#define _CHANNEL_C
/*-------------------------------------------------------------------*/
/* FORMAT I/O BUFFER DATA */
/*-------------------------------------------------------------------*/
static void format_iobuf_data( const RADR addr, BYTE *area, const DEVBLK *dev, const u_int len) /*@IWZ*/
{
BYTE *a; /* -> Byte in main storage */
u_int i, j, k; /* Array subscripts */
BYTE workarea[17]; /* Character String work */
k = MIN(len, sizeof(workarea)-1);
area[0] = '\0';
if (!dev->is_immed && k && addr <= dev->mainlim - k)
{
memcpy(workarea, dev->mainstor + addr, k);
a = workarea;
j = sprintf ((char *)area,
"=>%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X"
" %2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X ",
a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7],
a[8], a[9], a[10], a[11], a[12], a[13], a[14], a[15]);
/* Blank out unused area */
if (k != 16)
{
i = ((len + 1) * 2) + (len / 4);
memset(area + i, ' ', strlen((char *)area) - i);
}
/* Append translation */
prt_guest_to_host(a, &area[j], k);
}
} /* end function format_iobuf_data */
/*-------------------------------------------------------------------*/
/* DISPLAY CHANNEL COMMAND WORD AND DATA */
/*-------------------------------------------------------------------*/
static void display_ccw ( const DEVBLK *dev, const BYTE ccw[], const U32 addr, U32 count, const U8 flags )
{
BYTE area[64]; /* Data display area */
if ( flags & CCW_FLAGS_SKIP || ( ccw[0] & 0x0f ) == 0x08 )
count = 0;
format_iobuf_data( addr, area, dev, count );
WRMSG (HHC01315, "I", SSID_TO_LCSS(dev->ssid), dev->devnum,
ccw[0], ccw[1], ccw[2], ccw[3],
ccw[4], ccw[5], ccw[6], ccw[7], area);
} /* end function display_ccw */
/*-------------------------------------------------------------------*/
/* DISPLAY IDAW AND DATA */
/*-------------------------------------------------------------------*/
static void display_idaw ( const DEVBLK *dev, const BYTE type, const BYTE flag, const RADR addr, const U16 count )
{
BYTE area[64]; /* Data display area */
format_iobuf_data( addr, area, dev, count );
switch(type)
{
case PF_IDAW1:
WRMSG (HHC01302, "I", SSID_TO_LCSS(dev->ssid), dev->devnum, (U32)addr, count, area );
break;
case PF_IDAW2:
WRMSG (HHC01303, "I", SSID_TO_LCSS(dev->ssid), dev->devnum, (U64)addr, count, area );
break;
case PF_MIDAW:
WRMSG (HHC01301, "I", SSID_TO_LCSS(dev->ssid), dev->devnum, flag, count, (U64)addr, area );
}
} /* end function display_idaw */
/*-------------------------------------------------------------------*/
/* DISPLAY CHANNEL STATUS WORD */
/*-------------------------------------------------------------------*/
static void display_csw (const DEVBLK *dev, const BYTE csw[])
{
WRMSG (HHC01316, "I", SSID_TO_LCSS(dev->ssid), dev->devnum,
csw[4], csw[5], csw[6], csw[7],
csw[1], csw[2], csw[3]);
} /* end function display_csw */
/*-------------------------------------------------------------------*/
/* DISPLAY SUBCHANNEL STATUS WORD */
/*-------------------------------------------------------------------*/
static void display_scsw ( const DEVBLK *dev, const SCSW scsw)
{
WRMSG (HHC01317, "I", SSID_TO_LCSS(dev->ssid), dev->devnum,
scsw.flag0, scsw.flag1, scsw.flag2, scsw.flag3,
scsw.unitstat, scsw.chanstat,
scsw.count[0], scsw.count[1],
scsw.ccwaddr[0], scsw.ccwaddr[1],
scsw.ccwaddr[2], scsw.ccwaddr[3]);
} /* end function display_scsw */
/*-------------------------------------------------------------------*/
/* STORE CHANNEL ID */
/*-------------------------------------------------------------------*/
int stchan_id (REGS *regs, U16 chan)
{
U32 chanid; /* Channel identifier word */
int devcount = 0; /* #of devices on channel */
DEVBLK *dev; /* -> Device control block */
PSA_3XX *psa; /* -> Prefixed storage area */
/* Find a device on specified channel */
for (dev = sysblk.firstdev; dev != NULL; dev = dev->nextdev)
{
/* Skip the device if not on specified channel */
if ((dev->devnum & 0xFF00) != chan
|| (dev->pmcw.flag5 & PMCW5_V) == 0
#if defined(FEATURE_CHANNEL_SWITCHING)
|| regs->chanset != dev->chanset
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
)
continue;
/* Found device on the channel */
devcount++;
break;
} /* end for(dev) */
/* Exit with condition code 3 if no devices on channel */
if (devcount == 0)
return 3;
/* Construct the channel id word */
/* According to GA22-7000-4, Page 192, 2nd paragraph,
* channel 0 is a Byte Multiplexor.. Return STIDC data
* accordingly
* ISW 20080313
*/
if(!chan)
{
chanid = CHANNEL_MPX;
}
else
{
chanid = CHANNEL_BMX;
}
/* Store the channel id word at PSA+X'A8' */
psa = (PSA_3XX*)(regs->mainstor + regs->PX);
STORE_FW(psa->chanid, chanid);
/* Exit with condition code 0 indicating channel id stored */
return 0;
} /* end function stchan_id */
/*-------------------------------------------------------------------*/
/* TEST CHANNEL */
/*-------------------------------------------------------------------*/
int testch (REGS *regs, U16 chan)
{
DEVBLK *dev; /* -> Device control block */
int devcount = 0; /* Number of devices found */
int cc = 0; /* Returned condition code */
/* Scan devices on the channel */
for (dev = sysblk.firstdev; dev != NULL; dev = dev->nextdev)
{
/* Skip the device if not on specified channel */
if ((dev->devnum & 0xFF00) != chan
|| (dev->pmcw.flag5 & PMCW5_V) == 0
#if defined(FEATURE_CHANNEL_SWITCHING)
|| regs->chanset != dev->chanset
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
)
continue;
/* Increment device count on this channel */
devcount++;
/* Test for pending interrupt */
if (IOPENDING(dev))
{
cc = 1;
break;
}
}
/* Set condition code 3 if no devices found on the channel */
if (devcount == 0)
cc = 3;
return cc;
} /* end function testch */
/*-------------------------------------------------------------------*/
/* TEST I/O */
/*-------------------------------------------------------------------*/
int testio (REGS *regs, DEVBLK *dev, BYTE ibyte)
{
int cc; /* Condition code */
PSA_3XX *psa; /* -> Prefixed storage area */
IOINT *ioint=NULL;
UNREFERENCED(ibyte);
if (dev->ccwtrace || dev->ccwstep)
WRMSG (HHC01318, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
obtain_lock (&dev->lock);
/* Test device status and set condition code */
if ((dev->busy && dev->ioactive == DEV_SYS_LOCAL)
|| dev->startpending)
{
/* Set condition code 2 if device is busy */
cc = 2;
}
else
{
if (IOPENDING(dev))
{
/* Set condition code 1 if interrupt pending */
cc = 1;
/* Store the channel status word at PSA+X'40' */
psa = (PSA_3XX*)(regs->mainstor + regs->PX);
if (dev->pcipending)
{
memcpy (psa->csw, dev->pcicsw, 8);
ioint=&dev->pciioint;
}
else
{
if(dev->pending)
{
memcpy (psa->csw, dev->csw, 8);
ioint=&dev->ioint;
}
else
{
memcpy (psa->csw, dev->attncsw, 8);
ioint=&dev->attnioint;
}
}
/* Signal console thread to redrive select */
if (dev->console)
{
SIGNAL_CONSOLE_THREAD();
}
if (dev->ccwtrace || dev->ccwstep)
display_csw (dev, psa->csw);
}
else
{
/* Set condition code 1 if device is LCS CTC */
if ( dev->ctctype == CTC_LCS )
{
cc = 1;
dev->csw[4] = 0;
dev->csw[5] = 0;
psa = (PSA_3XX*)(regs->mainstor + regs->PX);
memcpy (psa->csw, dev->csw, 8);
if (dev->ccwtrace)
{
WRMSG (HHC01319, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
display_csw (dev, dev->csw);
}
}
else
/* Set condition code 0 if device is available */
cc = 0;
}
}
/* Dequeue the interrupt */
if(ioint)
DEQUEUE_IO_INTERRUPT(ioint);
release_lock (&dev->lock);
/* Update interrupt status */
if(ioint)
{
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
}
/* Return the condition code */
return cc;
} /* end function testio */
/*-------------------------------------------------------------------*/
/* HALT I/O */
/*-------------------------------------------------------------------*/
int haltio (REGS *regs, DEVBLK *dev, BYTE ibyte)
{
int cc; /* Condition code */
PSA_3XX *psa; /* -> Prefixed storage area */
int pending = 0; /* New interrupt pending */
UNREFERENCED(ibyte);
if (dev->ccwtrace || dev->ccwstep)
WRMSG (HHC01329, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
obtain_lock (&dev->lock);
/* Test device status and set condition code */
if (dev->busy)
{
/* Invoke the provided halt device routine @ISW */
/* if it has been provided by the handler @ISW */
/* code at init @ISW */
if(dev->hnd->halt!=NULL) /* @ISW */
{ /* @ISW */
dev->hnd->halt(dev); /* @ISW */
cc=0; /* @ISW */
} /* @ISW */
else
{
/* Set condition code 2 if device is busy */
cc = 2;
/* Tell channel and device to halt */
dev->scsw.flag2 |= SCSW2_FC_HALT;
/* Clear pending interrupts */
dev->pending = dev->pcipending = dev->attnpending = 0;
}
}
else if (!IOPENDING(dev) && dev->ctctype != CTC_LCS)
{
/* Set condition code 1 */
cc = 1;
/* Store the channel status word at PSA+X'40' */
psa = (PSA_3XX*)(regs->mainstor + regs->PX);
memcpy (psa->csw, dev->csw, 8);
/* Set pending interrupt */
dev->pending = pending = 1;
if (dev->ccwtrace || dev->ccwstep)
display_csw (dev, dev->csw);
}
else
{
/* Set cc 1 if interrupt is not pending and LCS CTC */
if ( dev->ctctype == CTC_LCS )
{
cc = 1;
dev->csw[4] = 0;
dev->csw[5] = 0;
psa = (PSA_3XX*)(regs->mainstor + regs->PX);
memcpy (psa->csw, dev->csw, 8);
if (dev->ccwtrace)
{
WRMSG (HHC01330, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
display_csw (dev, dev->csw);
}
}
else
/* Set condition code 0 if interrupt is pending */
cc = 0;
}
/* For 3270 device, clear any pending input */
if (dev->devtype == 0x3270)
{
dev->readpending = 0;
dev->rlen3270 = 0;
}
/* Signal console thread to redrive select */
if (dev->console)
{
SIGNAL_CONSOLE_THREAD();
}
/* Queue the interrupt */
if (pending)
QUEUE_IO_INTERRUPT (&dev->ioint);
release_lock (&dev->lock);
/* Update interrupt status */
if (pending)
{
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
}
/* Return the condition code */
return cc;
} /* end function haltio */
/*-------------------------------------------------------------------*/
/* CANCEL SUBCHANNEL */
/*-------------------------------------------------------------------*/
/* Input */
/* regs -> CPU register context */
/* dev -> Device control block */
/* Return value */
/* The return value is the condition code for the XSCH */
/* 0=start function cancelled (not yet implemented) */
/* 1=status pending (no action taken) */
/* 2=function not applicable */
/*-------------------------------------------------------------------*/
int cancel_subchan (REGS *regs, DEVBLK *dev)
{
int cc; /* Condition code */
UNREFERENCED(regs);
obtain_lock (&dev->lock);
#if defined(_FEATURE_IO_ASSIST)
if(SIE_MODE(regs)
&& (regs->siebk->zone != dev->pmcw.zone
|| !(dev->pmcw.flag27 & PMCW27_I)))
{
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_INST);
}
#endif
/* Check pending status */
if ((dev->pciscsw.flag3 & SCSW3_SC_PEND)
|| (dev->scsw.flag3 & SCSW3_SC_PEND)
|| (dev->attnscsw.flag3 & SCSW3_SC_PEND))
cc = 1;
else
{
cc = 2;
#if !defined(OPTION_FISHIO)
obtain_lock(&sysblk.ioqlock);
if(sysblk.ioq != NULL)
{
DEVBLK *tmp;
/* special case for head of queue */
if(sysblk.ioq == dev)
{
/* Remove device from the i/o queue */
sysblk.ioq = dev->nextioq;
cc = 0;
}
else
{
/* Search for device on i/o queue */
for(tmp = sysblk.ioq; tmp->nextioq != NULL && tmp->nextioq != dev; tmp = tmp->nextioq);
/* Remove from queue if found */
if(tmp->nextioq == dev)
{
tmp->nextioq = tmp->nextioq->nextioq;
cc = 0;
}
}
/* Reset the device */
if(!cc)
{
/* Terminate suspended channel program */
if (dev->scsw.flag3 & SCSW3_AC_SUSP)
{
dev->suspended = 0;
signal_condition (&dev->resumecond);
}
/* Reset the scsw */
dev->scsw.flag2 &= ~(SCSW2_AC_RESUM | SCSW2_FC_START | SCSW2_AC_START);
dev->scsw.flag3 &= ~(SCSW3_AC_SUSP);
/* Reset the device busy indicator */
dev->busy = dev->startpending = 0;
}
}
release_lock(&sysblk.ioqlock);
#endif /*!defined(OPTION_FISHIO)*/
}
release_lock (&dev->lock);
/* Return the condition code */
return cc;
} /* end function cancel_subchan */
/*-------------------------------------------------------------------*/
/* TEST SUBCHANNEL */
/*-------------------------------------------------------------------*/
/* Input */
/* regs -> CPU register context */
/* dev -> Device control block */
/* Output */
/* irb -> Interruption response block */
/* Return value */
/* The return value is the condition code for the TSCH */
/* instruction: 0=status was pending and is now cleared, */
/* 1=no status was pending. The IRB is updated in both cases. */
/*-------------------------------------------------------------------*/
int test_subchan (REGS *regs, DEVBLK *dev, IRB *irb)
{
int cc; /* Condition code */
#if defined(_FEATURE_IO_ASSIST)
UNREFERENCED(regs);
#endif
obtain_lock (&dev->lock);
#if defined(_FEATURE_IO_ASSIST)
if(SIE_MODE(regs)
&& (regs->siebk->zone != dev->pmcw.zone
|| !(dev->pmcw.flag27 & PMCW27_I)))
{
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_INST);
}
#endif
/* Return PCI SCSW if PCI status is pending */
if (dev->pciscsw.flag3 & SCSW3_SC_PEND)
{
#if defined(_FEATURE_IO_ASSIST)
/* For I/O assisted devices we must intercept if type B
status is present on the subchannel */
if(SIE_MODE(regs)
&& ( (regs->siebk->tschds & dev->pciscsw.unitstat)
|| (regs->siebk->tschsc & dev->pciscsw.chanstat) ) )
{
dev->pmcw.flag27 &= ~PMCW27_I;
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_IOINST);
}
#endif
/* Display the subchannel status word */
if (dev->ccwtrace || dev->ccwstep)
display_scsw (dev, dev->pciscsw);
/* Copy the PCI SCSW to the IRB */
irb->scsw = dev->pciscsw;
/* Clear the ESW and ECW in the IRB */
memset (&irb->esw, 0, sizeof(ESW));
irb->esw.lpum = 0x80;
memset (irb->ecw, 0, sizeof(irb->ecw));
/* Clear the pending PCI status */
dev->pciscsw.flag2 &= ~(SCSW2_FC | SCSW2_AC);
dev->pciscsw.flag3 &= ~(SCSW3_SC);
dev->pcipending = 0;
/* Dequeue the interrupt */
DEQUEUE_IO_INTERRUPT(&dev->pciioint);
release_lock (&dev->lock);
/* Update interrupt status */
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
/* Return condition code 0 to indicate status was pending */
return 0;
} /* end if(pcipending) */
/* Copy the subchannel status word to the IRB */
irb->scsw = dev->scsw;
/* Copy the extended status word to the IRB */
irb->esw = dev->esw;
/* Copy the extended control word to the IRB */
memcpy (irb->ecw, dev->ecw, sizeof(irb->ecw));
/* Test device status and set condition code */
if (dev->scsw.flag3 & SCSW3_SC_PEND)
{
#if defined(_FEATURE_IO_ASSIST)
/* For I/O assisted devices we must intercept if type B
status is present on the subchannel */
if(SIE_MODE(regs)
&& ( (regs->siebk->tschds & dev->scsw.unitstat)
|| (regs->siebk->tschsc & dev->scsw.chanstat) ) )
{
dev->pmcw.flag27 &= ~PMCW27_I;
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_IOINST);
}
#endif
/* Set condition code 0 for status pending */
cc = 0;
/* Display the subchannel status word */
if (dev->ccwtrace || dev->ccwstep)
display_scsw (dev, dev->scsw);
/* [14.3.13] If status is anything other than intermediate with
pending then clear the function control, activity control,
status control, and path not-operational bits in the SCSW */
if ((dev->scsw.flag3 & SCSW3_SC)
!= (SCSW3_SC_INTER | SCSW3_SC_PEND))
{
dev->scsw.flag2 &= ~(SCSW2_FC | SCSW2_AC);
dev->scsw.flag3 &= ~(SCSW3_AC_SUSP);
dev->scsw.flag1 &= ~(SCSW1_N);
}
else
{
/* [14.3.13] Clear the function control bits if function
code is halt and the channel program is suspended */
if ((dev->scsw.flag2 & SCSW2_FC_HALT)
&& (dev->scsw.flag3 & SCSW3_AC_SUSP))
dev->scsw.flag2 &= ~(SCSW2_FC);
/* [14.3.13] Clear the activity control bits if function
code is start+halt and channel program is suspended */
if ((dev->scsw.flag2 & (SCSW2_FC_START | SCSW2_FC_HALT))
== (SCSW2_FC_START | SCSW2_FC_HALT)
&& (dev->scsw.flag3 & SCSW3_AC_SUSP))
{
dev->scsw.flag2 &= ~(SCSW2_AC);
dev->scsw.flag3 &= ~(SCSW3_AC_SUSP);
dev->scsw.flag1 &= ~(SCSW1_N);
}
/* [14.3.13] Clear the resume pending bit if function code
is start without halt and channel program suspended */
if ((dev->scsw.flag2 & (SCSW2_FC_START | SCSW2_FC_HALT))
== SCSW2_FC_START
&& (dev->scsw.flag3 & SCSW3_AC_SUSP))
{
dev->scsw.flag2 &= ~(SCSW2_AC_RESUM);
dev->scsw.flag1 &= ~(SCSW1_N);
}
} /* end if(INTER+PEND) */
/* Clear the status bits in the SCSW */
dev->scsw.flag3 &= ~(SCSW3_SC);
}
else
{
/* Test device status and set condition code */
if (dev->attnscsw.flag3 & SCSW3_SC_PEND)
{
#if defined(_FEATURE_IO_ASSIST)
/* For I/O assisted devices we must intercept if type B
status is present on the subchannel */
if(SIE_MODE(regs)
&& ( (regs->siebk->tschds & dev->attnscsw.unitstat)
|| (regs->siebk->tschsc & dev->attnscsw.chanstat) ) )
{
dev->pmcw.flag27 &= ~PMCW27_I;
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_IOINST);
}
#endif
/* Set condition code 0 for status pending */
cc = 0;
/* Display the subchannel status word */
if (dev->ccwtrace || dev->ccwstep)
display_scsw (dev, dev->attnscsw);
/* Copy the ATTN SCSW to the IRB */
irb->scsw = dev->attnscsw;
/* Clear the ESW and ECW in the IRB */
memset (&irb->esw, 0, sizeof(ESW));
irb->esw.lpum = 0x80;
memset (irb->ecw, 0, sizeof(irb->ecw));
/* Clear the pending ATTN status */
dev->attnscsw.flag2 &= ~(SCSW2_FC | SCSW2_AC);
dev->attnscsw.flag3 &= ~(SCSW3_SC);
dev->attnpending = 0;
/* Dequeue the interrupt */
DEQUEUE_IO_INTERRUPT(&dev->attnioint);
release_lock (&dev->lock);
/* Update interrupt status */
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
/* Signal console thread to redrive select */
if (dev->console)
{
SIGNAL_CONSOLE_THREAD();
}
/* Return condition code 0 to indicate status was pending */
return 0;
}
else
{
/* Set condition code 1 if status not pending */
cc = 1;
}
}
/* Dequeue the interrupt */
DEQUEUE_IO_INTERRUPT(&dev->ioint);
release_lock (&dev->lock);
/* Update interrupt status */
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
/* Signal console thread to redrive select */
if (dev->console)
{
SIGNAL_CONSOLE_THREAD();
}
/* Return the condition code */
return cc;
} /* end function test_subchan */
/*-------------------------------------------------------------------*/
/* CLEAR SUBCHANNEL */
/*-------------------------------------------------------------------*/
/* Input */
/* regs -> CPU register context */
/* dev -> Device control block */
/*-------------------------------------------------------------------*/
void clear_subchan (REGS *regs, DEVBLK *dev)
{
int pending = 0;
UNREFERENCED(regs);
if (dev->ccwtrace || dev->ccwstep)
WRMSG (HHC01330, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
obtain_lock (&dev->lock);
#if defined(_FEATURE_IO_ASSIST)
if(SIE_MODE(regs)
&& (regs->siebk->zone != dev->pmcw.zone
|| !(dev->pmcw.flag27 & PMCW27_I)))
{
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_INST);
}
#endif
/* If the device is busy then signal the device to clear */
if ((dev->busy && dev->ioactive == DEV_SYS_LOCAL)
|| dev->startpending)
{
/* Set clear pending condition */
dev->scsw.flag2 |= SCSW2_FC_CLEAR | SCSW2_AC_CLEAR;
/* Signal the subchannel to resume if it is suspended */
if (dev->scsw.flag3 & SCSW3_AC_SUSP)
{
dev->scsw.flag2 |= SCSW2_AC_RESUM;
signal_condition (&dev->resumecond);
}
else
{
/* Invoke the provided halt device routine @ISW */
/* if it has been provided by the handler @ISW */
/* code at init @ISW */
if(dev->hnd->halt!=NULL) /* @ISW */
{ /* @ISW */
dev->hnd->halt(dev); /* @ISW */
} /* @ISW */
#if !defined(NO_SIGABEND_HANDLER)
else
{
if( dev->ctctype )
signal_thread(dev->tid, SIGUSR2);
}
#endif /*!defined(NO_SIGABEND_HANDLER)*/
}
}
else
{
/* [15.3.2] Perform clear function subchannel modification */
dev->pmcw.pom = 0xFF;
dev->pmcw.lpum = 0x00;
dev->pmcw.pnom = 0x00;
/* [15.3.3] Perform clear function signaling and completion */
dev->scsw.flag0 = 0;
dev->scsw.flag1 = 0;
dev->scsw.flag2 &= ~(SCSW2_FC | SCSW2_AC);
dev->scsw.flag2 |= SCSW2_FC_CLEAR;
dev->scsw.flag3 &= (~(SCSW3_AC | SCSW3_SC))&0xff;
dev->scsw.flag3 |= SCSW3_SC_PEND;
store_fw (dev->scsw.ccwaddr, 0);
dev->scsw.chanstat = 0;
dev->scsw.unitstat = 0;
store_hw (dev->scsw.count, 0);
dev->pcipending = 0;
dev->pending = 1;
pending = 1;
/* For 3270 device, clear any pending input */
if (dev->devtype == 0x3270)
{
dev->readpending = 0;
dev->rlen3270 = 0;
}
/* Signal console thread to redrive select */
if (dev->console)
{
SIGNAL_CONSOLE_THREAD();
}
}
/* Queue any pending i/o interrupt */
if (pending)
QUEUE_IO_INTERRUPT (&dev->ioint);
release_lock (&dev->lock);
/* Update interrupt status */
if (pending)
{
OBTAIN_INTLOCK(regs);
UPDATE_IC_IOPENDING();
RELEASE_INTLOCK(regs);
}
} /* end function clear_subchan */
/*-------------------------------------------------------------------*/
/* HALT SUBCHANNEL */
/*-------------------------------------------------------------------*/
/* Input */
/* regs -> CPU register context */
/* dev -> Device control block */
/* Return value */
/* The return value is the condition code for the HSCH */
/* instruction: 0=Halt initiated, 1=Non-intermediate status */
/* pending, 2=Busy */
/*-------------------------------------------------------------------*/
int halt_subchan (REGS *regs, DEVBLK *dev)
{
int pending = 0;
UNREFERENCED(regs);
if (dev->ccwtrace || dev->ccwstep)
WRMSG (HHC01332, "I", SSID_TO_LCSS(dev->ssid), dev->devnum);
obtain_lock (&dev->lock);
#if defined(_FEATURE_IO_ASSIST)
if(SIE_MODE(regs)
&& (regs->siebk->zone != dev->pmcw.zone
|| !(dev->pmcw.flag27 & PMCW27_I)))
{
release_lock (&dev->lock);
longjmp(regs->progjmp,SIE_INTERCEPT_INST);
}
#endif
/* Set condition code 1 if subchannel is status pending alone or
is status pending with alert, primary, or secondary status */
if ((dev->scsw.flag3 & SCSW3_SC) == SCSW3_SC_PEND
|| ((dev->scsw.flag3 & SCSW3_SC_PEND)
&& (dev->scsw.flag3 &
(SCSW3_SC_ALERT | SCSW3_SC_PRI | SCSW3_SC_SEC))))
{
if (dev->ccwtrace || dev->ccwstep)
WRMSG (HHC01300, "I", SSID_TO_LCSS(dev->ssid), dev->devnum, 1);
release_lock (&dev->lock);
return 1;
}
/* Set condition code 2 if the halt function or the clear