forked from tonioni/WinUAE
/
65c02core.cpp
2493 lines (2094 loc) · 96.2 KB
/
65c02core.cpp
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/*
* 65C02core.c - 65C02/65SC02 emulation core.
*
* Written by
* Marco van den Heuvel <blackystardust68@yahoo.com>
*
* This file is part of VICE, the Versatile Commodore Emulator.
* See README for copyright notice.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307 USA.
*
*/
/* This file is included by the following CPU definition files:
- drivecpu65c02.c
*/
/* any CPU definition file that includes this file needs to do the following:
*
* - define reg_a as 8bit.
* - define reg_x as 8bit.
* - define reg_y as 8bit.
* - define reg_pc as 16bit.
* - define reg_sp as 8bit.
* - define reg_p as 8bit
* - define the cpu being emulated in a var 'cpu_type' (CPU_WDC65C02, CPU_R65C02, CPU_65SC02).
* - define a function to handle the WDC65C02 STP opcode (WDC_STP(void)).
* - define a function to handle the WDC65C02 WAI opcode (WDC_WAI(void)).
*
*/
/* still to check and possibly fix:
*
* - BRK does get interrupted by an IRQ/NMI on the 65(S)C02?
*/
#ifndef CPU_STR
#define CPU_STR "65(S)C02 CPU"
#endif
//#include "traps.h"
/* To avoid 'magic' numbers, we will use the following defines. */
#define CYCLES_0 0
#define CYCLES_1 1
#define CYCLES_2 2
#define CYCLES_3 3
#define CYCLES_4 4
#define CYCLES_5 5
#define SIZE_1 1
#define SIZE_2 2
#define SIZE_3 3
#define BIT_0 0
#define BIT_1 1
#define BIT_2 2
#define BIT_3 3
#define BIT_4 4
#define BIT_5 5
#define BIT_6 6
#define BIT_7 7
#define IRQ_CYCLES 7
#define NMI_CYCLES 7
#define RESET_CYCLES 6
/* ------------------------------------------------------------------------- */
/* Backup for non-6509 CPUs. */
#ifndef LOAD_IND
#define LOAD_IND(a) LOAD(a)
#endif
#ifndef STORE_IND
#define STORE_IND(a, b) STORE(a, b)
#endif
/* ------------------------------------------------------------------------- */
/* Backup for non-variable cycle CPUs. */
#ifndef CLK_ADD
#define CLK_ADD(clock, amount) clock += amount
#endif
#ifndef REWIND_FETCH_OPCODE
#define REWIND_FETCH_OPCODE(clock, amount) clock -= amount
#endif
/* ------------------------------------------------------------------------- */
/* Hook for additional delay. */
#ifndef CPU_DELAY_CLK
#define CPU_DELAY_CLK
#endif
#ifndef CPU_REFRESH_CLK
#define CPU_REFRESH_CLK
#endif
/* ------------------------------------------------------------------------- */
#ifndef CYCLE_EXACT_ALARM
#define PROCESS_ALARMS \
while (CLK >= alarm_context_next_pending_clk(ALARM_CONTEXT)) { \
alarm_context_dispatch(ALARM_CONTEXT, CLK); \
CPU_DELAY_CLK \
}
#else
#define PROCESS_ALARMS
#endif
/* ------------------------------------------------------------------------- */
#define LOCAL_SET_NZ(val) (flag_z = flag_n = (val))
#define LOCAL_SET_OVERFLOW(val) \
do { \
if (val) { \
reg_p |= P_OVERFLOW; \
} else { \
reg_p &= ~P_OVERFLOW; \
} \
} while (0)
#define LOCAL_SET_BREAK(val) \
do { \
if (val) { \
reg_p |= P_BREAK; \
} else { \
reg_p &= ~P_BREAK; \
} \
} while (0)
#define LOCAL_SET_DECIMAL(val) \
do { \
if (val) { \
reg_p |= P_DECIMAL; \
} else { \
reg_p &= ~P_DECIMAL; \
} \
} while (0)
#define LOCAL_SET_INTERRUPT(val) \
do { \
if (val) { \
reg_p |= P_INTERRUPT; \
} else { \
reg_p &= ~P_INTERRUPT; \
} \
} while (0)
#define LOCAL_SET_CARRY(val) \
do { \
if (val) { \
reg_p |= P_CARRY; \
} else { \
reg_p &= ~P_CARRY; \
} \
} while (0)
#define LOCAL_SET_SIGN(val) (flag_n = (val) ? 0x80 : 0)
#define LOCAL_SET_ZERO(val) (flag_z = !(val))
#define LOCAL_SET_STATUS(val) (reg_p = ((val) & ~(P_ZERO | P_SIGN)), \
LOCAL_SET_ZERO((val) & P_ZERO), \
flag_n = (val))
#define LOCAL_OVERFLOW() (reg_p & P_OVERFLOW)
#define LOCAL_BREAK() (reg_p & P_BREAK)
#define LOCAL_DECIMAL() (reg_p & P_DECIMAL)
#define LOCAL_INTERRUPT() (reg_p & P_INTERRUPT)
#define LOCAL_CARRY() (reg_p & P_CARRY)
#define LOCAL_SIGN() (flag_n & 0x80)
#define LOCAL_ZERO() (!flag_z)
#define LOCAL_STATUS() (reg_p | (flag_n & 0x80) | P_UNUSED \
| (LOCAL_ZERO() ? P_ZERO : 0))
#ifdef LAST_OPCODE_INFO
/* If requested, gather some info about the last executed opcode for timing
purposes. */
/* Remember the number of the last opcode. By default, the opcode does not
delay interrupt and does not change the I flag. */
#define SET_LAST_OPCODE(x) OPINFO_SET(LAST_OPCODE_INFO, (x), 0, 0, 0)
/* Remember that the last opcode delayed a pending IRQ or NMI by one cycle. */
#define OPCODE_DELAYS_INTERRUPT() OPINFO_SET_DELAYS_INTERRUPT(LAST_OPCODE_INFO, 1)
/* Remember that the last opcode changed the I flag from 0 to 1, so we have
to dispatch an IRQ even if the I flag is 0 when we check it. */
#define OPCODE_DISABLES_IRQ() OPINFO_SET_DISABLES_IRQ(LAST_OPCODE_INFO, 1)
/* Remember that the last opcode changed the I flag from 1 to 0, so we must
not dispatch an IRQ even if the I flag is 1 when we check it. */
#define OPCODE_ENABLES_IRQ() OPINFO_SET_ENABLES_IRQ(LAST_OPCODE_INFO, 1)
#else
/* Info about the last opcode is not needed. */
#define SET_LAST_OPCODE(x)
#define OPCODE_DELAYS_INTERRUPT()
#define OPCODE_DISABLES_IRQ()
#define OPCODE_ENABLES_IRQ()
#endif
#ifdef LAST_OPCODE_ADDR
#define SET_LAST_ADDR(x) LAST_OPCODE_ADDR = (x)
#else
#error "please define LAST_OPCODE_ADDR"
#endif
#ifndef DRIVE_CPU
/* Export the local version of the registers. */
#define EXPORT_REGISTERS() \
do { \
GLOBAL_REGS.pc = reg_pc; \
GLOBAL_REGS.a = reg_a; \
GLOBAL_REGS.x = reg_x; \
GLOBAL_REGS.y = reg_y; \
GLOBAL_REGS.sp = reg_sp; \
GLOBAL_REGS.p = reg_p; \
GLOBAL_REGS.n = flag_n; \
GLOBAL_REGS.z = flag_z; \
} while (0)
/* Import the public version of the registers. */
#define IMPORT_REGISTERS() \
do { \
reg_a = GLOBAL_REGS.a; \
reg_x = GLOBAL_REGS.x; \
reg_y = GLOBAL_REGS.y; \
reg_sp = GLOBAL_REGS.sp; \
reg_p = GLOBAL_REGS.p; \
flag_n = GLOBAL_REGS.n; \
flag_z = GLOBAL_REGS.z; \
bank_start = bank_limit = 0; /* prevent caching */ \
JUMP(GLOBAL_REGS.pc); \
} while (0)
#else /* DRIVE_CPU */
#define IMPORT_REGISTERS()
#define EXPORT_REGISTERS()
#endif /* !DRIVE_CPU */
/* Stack operations. */
#ifndef PUSH
#define PUSH(val) ((PAGE_ONE)[(reg_sp--)] = ((BYTE)(val)))
#endif
#ifndef PULL
#define PULL() ((PAGE_ONE)[(++reg_sp)])
#endif
#ifdef DEBUG
#define TRACE_NMI(clk) \
do { \
if (TRACEFLG) { \
debug_nmi(CPU_INT_STATUS, (clk)); \
} \
} while (0)
#define TRACE_IRQ(clk) \
do { \
if (TRACEFLG) { \
debug_irq(CPU_INT_STATUS, (clk)); \
} \
} while (0)
#define TRACE_BRK() \
do { \
if (TRACEFLG) { \
debug_text("*** BRK"); \
} \
} while (0)
#else
#define TRACE_NMI(clk)
#define TRACE_IRQ(clk)
#define TRACE_BRK()
#endif
/* Perform the interrupts in `int_kind'. If we have both NMI and IRQ,
execute NMI. NMI can _not_ take over an in progress IRQ. */
/* FIXME: LOCAL_STATUS() should check byte ready first. */
#define DO_INTERRUPT(int_kind) \
do { \
BYTE ik = (int_kind); \
\
if (ik & (IK_IRQ | IK_IRQPEND | IK_NMI)) { \
if ((ik & IK_NMI) \
&& interrupt_check_nmi_delay(CPU_INT_STATUS, CLK)) { \
TRACE_NMI(CLK); \
if (monitor_mask[CALLER] & (MI_STEP)) { \
monitor_check_icount_interrupt(); \
} \
interrupt_ack_nmi(CPU_INT_STATUS); \
if (NMI_CYCLES == 7) { \
LOAD(reg_pc); /* dummy reads */ \
CLK_ADD(CLK, 1); \
LOAD(reg_pc); \
CLK_ADD(CLK, 1); \
} \
LOCAL_SET_BREAK(0); \
PUSH(reg_pc >> 8); \
PUSH(reg_pc & 0xff); \
CLK_ADD(CLK, 2); \
PUSH(LOCAL_STATUS()); \
CLK_ADD(CLK, 1); \
LOCAL_SET_DECIMAL(0); \
LOCAL_SET_INTERRUPT(1); \
JUMP(LOAD_ADDR(0xfffa)); \
SET_LAST_OPCODE(0); \
CLK_ADD(CLK, 2); \
} \
if ((ik & (IK_IRQ | IK_IRQPEND)) && (!LOCAL_INTERRUPT() || OPINFO_DISABLES_IRQ(LAST_OPCODE_INFO)) \
&& interrupt_check_irq_delay(CPU_INT_STATUS, CLK)) { \
TRACE_IRQ(CLK); \
if (monitor_mask[CALLER] & (MI_STEP)) { \
monitor_check_icount_interrupt(); \
} \
interrupt_ack_irq(CPU_INT_STATUS); \
if (NMI_CYCLES == 7) { \
LOAD(reg_pc); /* dummy reads */ \
CLK_ADD(CLK, 1); \
LOAD(reg_pc); \
CLK_ADD(CLK, 1); \
} \
LOCAL_SET_BREAK(0); \
PUSH(reg_pc >> 8); \
PUSH(reg_pc & 0xff); \
CLK_ADD(CLK, 2); \
PUSH(LOCAL_STATUS()); \
CLK_ADD(CLK, 1); \
LOCAL_SET_DECIMAL(0); \
LOCAL_SET_INTERRUPT(1); \
JUMP(LOAD_ADDR(0xfffe)); \
SET_LAST_OPCODE(0); \
CLK_ADD(CLK, 2); \
} \
} \
if (ik & (IK_TRAP | IK_RESET)) { \
if (ik & IK_TRAP) { \
EXPORT_REGISTERS(); \
interrupt_do_trap(CPU_INT_STATUS, (WORD)reg_pc); \
IMPORT_REGISTERS(); \
if (CPU_INT_STATUS->global_pending_int & IK_RESET) { \
ik |= IK_RESET; \
} \
} \
if (ik & IK_RESET) { \
interrupt_ack_reset(CPU_INT_STATUS); \
cpu65c02_reset(); \
bank_start = bank_limit = 0; /* prevent caching */ \
JUMP(LOAD_ADDR(0xfffc)); \
DMA_ON_RESET; \
} \
} \
if (ik & (IK_MONITOR | IK_DMA)) { \
if (ik & IK_MONITOR) { \
if (monitor_force_import(CALLER)) { \
IMPORT_REGISTERS(); \
} \
if (monitor_mask[CALLER]) { \
EXPORT_REGISTERS(); \
} \
if (monitor_mask[CALLER] & (MI_STEP)) { \
monitor_check_icount((WORD)reg_pc); \
IMPORT_REGISTERS(); \
} \
if (monitor_mask[CALLER] & (MI_BREAK)) { \
if (monitor_check_breakpoints(CALLER, (WORD)reg_pc)) { \
monitor_startup(CALLER); \
IMPORT_REGISTERS(); \
} \
} \
if (monitor_mask[CALLER] & (MI_WATCH)) { \
monitor_check_watchpoints(LAST_OPCODE_ADDR, (WORD)reg_pc); \
IMPORT_REGISTERS(); \
} \
} \
if (ik & IK_DMA) { \
EXPORT_REGISTERS(); \
DMA_FUNC; \
interrupt_ack_dma(CPU_INT_STATUS); \
IMPORT_REGISTERS(); \
} \
} \
} while (0)
/* ------------------------------------------------------------------------- */
/* Addressing modes. For convenience, page boundary crossing cycles and
``idle'' memory reads are handled here as well. */
#define LOAD_ABS(addr) LOAD(addr)
#define LOAD_ABS_X(addr) \
((((addr) & 0xff) + reg_x) > 0xff \
? (LOAD(reg_pc + 2), \
CLK_ADD(CLK, CYCLES_1), \
LOAD((addr) + reg_x)) \
: LOAD((addr) + reg_x))
#define LOAD_ABS_X_RMW(addr) \
(LOAD(reg_pc + 2), \
CLK_ADD(CLK, CYCLES_1), \
LOAD((addr) + reg_x))
#define LOAD_ABS_Y(addr) \
((((addr) & 0xff) + reg_y) > 0xff \
? (LOAD(reg_pc + 2), \
CLK_ADD(CLK, CYCLES_1), \
LOAD((addr) + reg_y)) \
: LOAD((addr) + reg_y))
#define LOAD_INDIRECT(addr) (CLK_ADD(CLK, CYCLES_2), LOAD(LOAD_ZERO_ADDR((addr))))
#define LOAD_IND_X(addr) (CLK_ADD(CLK, CYCLES_3), LOAD(LOAD_ZERO_ADDR((addr) + reg_x)))
#define LOAD_IND_Y(addr) \
(CLK_ADD(CLK, CYCLES_2), ((LOAD_ZERO_ADDR((addr)) & 0xff) + reg_y) > 0xff \
? (LOAD(reg_pc + 1), \
CLK_ADD(CLK, CYCLES_1), \
LOAD(LOAD_ZERO_ADDR((addr)) + reg_y)) \
: LOAD(LOAD_ZERO_ADDR((addr)) + reg_y))
#define LOAD_ZERO_X(addr) (LOAD_ZERO((addr) + reg_x))
#define LOAD_ZERO_Y(addr) (LOAD_ZERO((addr) + reg_y))
#define LOAD_IND_Y_BANK(addr) \
(CLK_ADD(CLK, CYCLES_2), ((LOAD_ZERO_ADDR((addr)) & 0xff) + reg_y) > 0xff \
? (LOAD(reg_pc + 1), \
CLK_ADD(CLK, CYCLES_1), \
LOAD_IND(LOAD_ZERO_ADDR((addr)) + reg_y)) \
: LOAD_IND(LOAD_ZERO_ADDR((addr)) + reg_y))
#define STORE_ABS(addr, value) \
do { \
STORE((addr), (value)); \
} while (0)
#define STORE_ABS_RRW(addr, value) \
do { \
LOAD(addr); \
CLK_ADD(CLK, CYCLES_1); \
STORE(addr, value); \
CLK_ADD(CLK, CYCLES_1); \
} while (0)
#define STORE_ABS_X(addr, value) \
do { \
LOAD(reg_pc - 1); \
CLK_ADD(CLK, CYCLES_1); \
STORE((addr) + reg_x, (value)); \
CLK_ADD(CLK, CYCLES_1); \
} while (0)
#define STORE_ABS_X_RRW(addr, value) \
do { \
LOAD((addr) + reg_x); \
CLK_ADD(CLK, CYCLES_1); \
STORE((addr) + reg_x, (value)); \
CLK_ADD(CLK, CYCLES_1); \
} while (0)
#define STORE_ABS_Y(addr, value) \
do { \
LOAD(reg_pc - 1); \
CLK_ADD(CLK, CYCLES_1); \
STORE((addr) + reg_y, (value)); \
CLK_ADD(CLK, CYCLES_1); \
} while (0)
#define INC_PC(value) (reg_pc += (value))
/* ------------------------------------------------------------------------- */
/* Opcodes. */
/*
A couple of caveats about PC:
- the VIC-II emulation requires PC to be incremented before the first
write access (this is not (very) important when writing to the zero
page);
- `p0', `p1' and `p2' can only be used *before* incrementing PC: some
machines (eg. the C128) might depend on this.
*/
#define ADC(value, clk_inc, pc_inc) \
do { \
unsigned int tmp_value; \
unsigned int tmp, tmp2; \
\
tmp_value = (value); \
CLK_ADD(CLK, (clk_inc)); \
\
if (LOCAL_DECIMAL()) { \
tmp = (reg_a & 0xf) + (tmp_value & 0xf) + LOCAL_CARRY(); \
tmp2 = (reg_a & 0xf0) + (tmp_value & 0xf0); \
if (tmp > 9) { \
tmp2 += 0x10; \
tmp += 6; \
} \
LOCAL_SET_OVERFLOW(~(reg_a ^ tmp_value) & (reg_a ^ tmp) & 0x80); \
if (tmp2 > 0x90) { \
tmp2 += 0x60; \
} \
LOCAL_SET_CARRY(tmp2 & 0xff00); \
tmp = (tmp & 0xf) + (tmp2 & 0xf0); \
LOCAL_SET_NZ(tmp); \
LOAD(reg_pc + pc_inc - 1); \
CLK_ADD(CLK, CYCLES_1); \
} else { \
tmp = tmp_value + reg_a + LOCAL_CARRY(); \
LOCAL_SET_NZ(tmp & 0xff); \
LOCAL_SET_OVERFLOW(!((reg_a ^ tmp_value) & 0x80) && ((reg_a ^ tmp) & 0x80)); \
LOCAL_SET_CARRY(tmp > 0xff); \
} \
reg_a = tmp; \
INC_PC(pc_inc); \
} while (0)
#define AND(value, clk_inc, pc_inc) \
do { \
reg_a = (BYTE)(reg_a & (value)); \
LOCAL_SET_NZ(reg_a); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define ASL(addr, clk_inc, pc_inc, load_func, store_func) \
do { \
unsigned int tmp_value, tmp_addr; \
\
tmp_addr = (addr); \
tmp_value = load_func(tmp_addr); \
LOCAL_SET_CARRY(tmp_value & 0x80); \
tmp_value = (tmp_value << 1) & 0xff; \
LOCAL_SET_NZ(tmp_value); \
INC_PC(pc_inc); \
CLK_ADD(CLK, clk_inc); \
store_func(tmp_addr, tmp_value); \
} while (0)
#define ASL_A() \
do { \
LOCAL_SET_CARRY(reg_a & 0x80); \
reg_a = reg_a << 1; \
LOCAL_SET_NZ(reg_a); \
INC_PC(SIZE_1); \
} while (0)
#define BBR(bit) \
do { \
unsigned int tmp, tmp_addr; \
unsigned int dest_addr; \
BYTE value; \
\
if (cpu_type == CPU_65SC02) { \
NOOP_IMM(SIZE_1); \
} else { \
tmp_addr = LOAD(reg_pc + 1); \
CLK_ADD(CLK, CYCLES_1); \
value = LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
tmp = LOAD_ZERO(tmp_addr) & (1 << bit); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_3); \
LOAD(reg_pc); \
CLK_ADD(CLK, CYCLES_1); \
if (!tmp) { \
dest_addr = reg_pc + (signed char)(value); \
OPCODE_DELAYS_INTERRUPT(); \
JUMP(dest_addr & 0xffff); \
} \
} \
} while (0)
#define BBS(bit) \
do { \
unsigned int tmp, tmp_addr; \
unsigned int dest_addr; \
BYTE value; \
\
if (cpu_type == CPU_65SC02) { \
NOOP_IMM(SIZE_1); \
} else { \
tmp_addr = LOAD(reg_pc + 1); \
CLK_ADD(CLK, CYCLES_1); \
value = LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
tmp = LOAD_ZERO(tmp_addr) & (1 << bit); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_3); \
LOAD(reg_pc); \
CLK_ADD(CLK, CYCLES_1); \
\
if (tmp) { \
dest_addr = reg_pc + (signed char)(value); \
OPCODE_DELAYS_INTERRUPT(); \
JUMP(dest_addr & 0xffff); \
} \
} \
} while (0)
#define BIT(value, clk_inc, pc_inc) \
do { \
unsigned int tmp; \
\
tmp = (value); \
CLK_ADD(CLK, clk_inc); \
LOCAL_SET_SIGN(tmp & 0x80); \
LOCAL_SET_OVERFLOW(tmp & 0x40); \
LOCAL_SET_ZERO(!(tmp & reg_a)); \
INC_PC(pc_inc); \
} while (0)
#define BIT_IMM(value) \
do { \
unsigned int tmp; \
\
tmp = (value); \
LOCAL_SET_ZERO(!(tmp & reg_a)); \
INC_PC(SIZE_2); \
} while (0)
#define BRANCH(cond, value) \
do { \
unsigned int dest_addr = 0; \
INC_PC(SIZE_2); \
\
if (cond) { \
dest_addr = reg_pc + (signed char)(value); \
\
LOAD(reg_pc); \
CLK_ADD(CLK, CYCLES_1); \
if ((reg_pc ^ dest_addr) & 0xff00) { \
LOAD(reg_pc); \
CLK_ADD(CLK, CYCLES_1); \
} else { \
OPCODE_DELAYS_INTERRUPT(); \
} \
JUMP(dest_addr & 0xffff); \
} \
} while (0)
#define BRK() \
do { \
EXPORT_REGISTERS(); \
TRACE_BRK(); \
INC_PC(SIZE_2); \
LOCAL_SET_BREAK(1); \
PUSH(reg_pc >> 8); \
PUSH(reg_pc & 0xff); \
CLK_ADD(CLK, CYCLES_2); \
PUSH(LOCAL_STATUS()); \
CLK_ADD(CLK, CYCLES_1); \
LOCAL_SET_DECIMAL(0); \
LOCAL_SET_INTERRUPT(1); \
JUMP(LOAD_ADDR(0xfffe)); \
CLK_ADD(CLK, CYCLES_2); \
} while (0)
#define CLC() \
do { \
INC_PC(SIZE_1); \
LOCAL_SET_CARRY(0); \
} while (0)
#define CLD() \
do { \
INC_PC(SIZE_1); \
LOCAL_SET_DECIMAL(0); \
} while (0)
#define CLI() \
do { \
INC_PC(SIZE_1); \
if (LOCAL_INTERRUPT()) { \
OPCODE_ENABLES_IRQ(); \
} \
LOCAL_SET_INTERRUPT(0); \
} while (0)
#define CLV() \
do { \
INC_PC(SIZE_1); \
LOCAL_SET_OVERFLOW(0); \
} while (0)
#define CMP(value, clk_inc, pc_inc) \
do { \
unsigned int tmp; \
\
tmp = reg_a - (value); \
LOCAL_SET_CARRY(tmp < 0x100); \
LOCAL_SET_NZ(tmp & 0xff); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define CPX(value, clk_inc, pc_inc) \
do { \
unsigned int tmp; \
\
tmp = reg_x - (value); \
LOCAL_SET_CARRY(tmp < 0x100); \
LOCAL_SET_NZ(tmp & 0xff); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define CPY(value, clk_inc, pc_inc) \
do { \
unsigned int tmp; \
\
tmp = reg_y - (value); \
LOCAL_SET_CARRY(tmp < 0x100); \
LOCAL_SET_NZ(tmp & 0xff); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define DEA() \
do { \
reg_a--; \
LOCAL_SET_NZ(reg_a); \
INC_PC(SIZE_1); \
} while (0)
#define DEC(addr, clk_inc, pc_inc, load_func, store_func) \
do { \
unsigned int tmp, tmp_addr; \
\
tmp_addr = (addr); \
tmp = load_func(tmp_addr); \
tmp = (tmp - 1) & 0xff; \
LOCAL_SET_NZ(tmp); \
INC_PC(pc_inc); \
CLK_ADD(CLK, (clk_inc)); \
store_func(tmp_addr, tmp); \
} while (0)
#define DEX() \
do { \
reg_x--; \
LOCAL_SET_NZ(reg_x); \
INC_PC(SIZE_1); \
} while (0)
#define DEY() \
do { \
reg_y--; \
LOCAL_SET_NZ(reg_y); \
INC_PC(SIZE_1); \
} while (0)
#define EOR(value, clk_inc, pc_inc) \
do { \
reg_a = (BYTE)(reg_a ^ (value)); \
LOCAL_SET_NZ(reg_a); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define INA() \
do { \
reg_a++; \
LOCAL_SET_NZ(reg_a); \
INC_PC(SIZE_1); \
} while (0)
#define INC(addr, clk_inc, pc_inc, load_func, store_func) \
do { \
unsigned int tmp, tmp_addr; \
\
tmp_addr = (addr); \
tmp = (load_func(tmp_addr) + 1) & 0xff; \
LOCAL_SET_NZ(tmp); \
INC_PC(pc_inc); \
CLK_ADD(CLK, (clk_inc)); \
store_func(tmp_addr, tmp); \
} while (0)
#define INX() \
do { \
reg_x++; \
LOCAL_SET_NZ(reg_x); \
INC_PC(SIZE_1); \
} while (0)
#define INY() \
do { \
reg_y++; \
LOCAL_SET_NZ(reg_y); \
INC_PC(SIZE_1); \
} while (0)
/* The 0x02 NOP opcode is also used to patch the ROM. The function trap_handler()
returns nonzero if this is not a patch, but a `real' NOP instruction. */
#define NOP_02() \
do { \
DWORD trap_result; \
EXPORT_REGISTERS(); \
if (!ROM_TRAP_ALLOWED() \
|| (trap_result = ROM_TRAP_HANDLER()) == (DWORD)-1) { \
NOOP_IMM(SIZE_2); \
} else { \
if (trap_result) { \
REWIND_FETCH_OPCODE(CLK, CYCLES_2); \
SET_OPCODE(trap_result); \
IMPORT_REGISTERS(); \
goto trap_skipped; \
} else { \
IMPORT_REGISTERS(); \
} \
} \
} while (0)
#define JMP(addr) \
do { \
JUMP(addr); \
} while (0)
#define JMP_IND() \
do { \
WORD dest_addr; \
dest_addr = LOAD(p2); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
dest_addr |= (LOAD((p2 + 1) & 0xffff) << 8); \
CLK_ADD(CLK, CYCLES_1); \
JUMP(dest_addr); \
} while (0)
#define JMP_IND_X() \
do { \
WORD dest_addr; \
dest_addr = LOAD((p2 + reg_x) & 0xffff); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
dest_addr |= (LOAD((p2 + reg_x + 1) & 0xffff) << 8); \
CLK_ADD(CLK, CYCLES_1); \
JUMP(dest_addr); \
} while (0)
#define JSR() \
do { \
unsigned int tmp_addr; \
\
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_2); \
CLK_ADD(CLK, CYCLES_2); \
PUSH(((reg_pc) >> 8) & 0xff); \
PUSH((reg_pc) & 0xff); \
tmp_addr = (p1 | (LOAD(reg_pc) << 8)); \
CLK_ADD(CLK, CYCLES_1); \
JUMP(tmp_addr); \
} while (0)
#define LDA(value, clk_inc, pc_inc) \
do { \
reg_a = (BYTE)(value); \
CLK_ADD(CLK, (clk_inc)); \
LOCAL_SET_NZ(reg_a); \
INC_PC(pc_inc); \
} while (0)
#define LDX(value, clk_inc, pc_inc) \
do { \
reg_x = (BYTE)(value); \
LOCAL_SET_NZ(reg_x); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define LDY(value, clk_inc, pc_inc) \
do { \
reg_y = (BYTE)(value); \
LOCAL_SET_NZ(reg_y); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define LSR(addr, clk_inc, pc_inc, load_func, store_func) \
do { \
unsigned int tmp, tmp_addr; \
\
tmp_addr = (addr); \
tmp = load_func(tmp_addr); \
LOCAL_SET_CARRY(tmp & 0x01); \
tmp >>= 1; \
LOCAL_SET_NZ(tmp); \
INC_PC(pc_inc); \
CLK_ADD(CLK, clk_inc); \
store_func(tmp_addr, tmp); \
} while (0)
#define LSR_A() \
do { \
LOCAL_SET_CARRY(reg_a & 0x01); \
reg_a = reg_a >> 1; \
LOCAL_SET_NZ(reg_a); \
INC_PC(SIZE_1); \
} while (0)
#define ORA(value, clk_inc, pc_inc) \
do { \
reg_a = (BYTE)(reg_a | (value)); \
LOCAL_SET_NZ(reg_a); \
CLK_ADD(CLK, (clk_inc)); \
INC_PC(pc_inc); \
} while (0)
#define NOOP(clk_inc, pc_inc) (CLK_ADD(CLK, (clk_inc)), INC_PC(pc_inc))
#define NOOP_IMM(pc_inc) INC_PC(pc_inc)
#define NOOP_ZP() \
do { \
LOAD_ZERO(p1); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_2); \
} while (0)
#define NOOP_ZP_X() \
do { \
LOAD_ZERO(p1); \
CLK_ADD(CLK, CYCLES_1); \
LOAD_ZERO(p1 + reg_x); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_2); \
} while (0)
#define NOOP_ABS() \
do { \
LOAD(p2); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_3); \
} while (0)
#define NOOP_5C() \
do { \
LOAD(p2); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
LOAD(reg_pc + 2); \
CLK_ADD(CLK, CYCLES_1); \
INC_PC(SIZE_3); \
} while (0)
#define NOP() NOOP_IMM(SIZE_1)
#define PHA() \
do { \
CLK_ADD(CLK, CYCLES_1); \
PUSH(reg_a); \
INC_PC(SIZE_1); \
} while (0)
#define PHP() \
do { \
CLK_ADD(CLK, CYCLES_1); \
PUSH(LOCAL_STATUS() | P_BREAK); \
INC_PC(SIZE_1); \
} while (0)
#define PHX() \
do { \
CLK_ADD(CLK, CYCLES_1); \
PUSH(reg_x); \
INC_PC(SIZE_1); \
} while (0)
#define PHY() \
do { \
CLK_ADD(CLK, CYCLES_1); \
PUSH(reg_y); \
INC_PC(SIZE_1); \