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Ability to change the overall gain, fi and fd corner frequency separately
One needs to set P, I and D then get a set of kp=P/4096, ki=I/0.1s and kd=D / (2^6 * 125e6). However, in PID tuning use case, people usually want to change kp, fi, fd separately, corner frequencies fi = 4096/PI10 Hz, fd = P/4096/D2^6125e6 Hz. But if you change P, fi and fp will change. Better to provide an option for user to input L(f) = kp * (1 + fi / f + fd * f), kp, fi, fd are free parameters.
Limited corner frequencies
If I set P = 100, the lowest fi = 410Hz because minimum I = 1, the lowest fd = 23.8kHz because max D = 8191. But this might be a hardware limit which is hard to improve. We can find external gain to bypass it.
Add a D gain limit
See my measurement of linien transfer function on a VNA below. The D gain goes up all the way to >18MHz then it drops. But due to the latency, D gain cannot provide phase lead >2MHz, extra gain only makes the loop unstable (in my lock, I observe 500kHz oscillation). It is better to have a D gain limit that can be tuned.
We can add external filters to do this. This is just a plus.
Add an I gain limit
I gain limit can help with 1. some actuators like diode current in ECDL cannot take too much gain. 2. limited gain at DC makes the offset compensation easier to tune. See the red line in the above figure.
We can add external filters to do this. This is just a plus.
I know this part might be too much for a free project and they might be hard because it depends on redpid (?). I just want to provide some ideas according to my locking experience to make the project more powerful. :)
To be continued...
The text was updated successfully, but these errors were encountered:
Thank you for this issue and sharing your measurements.
Just as a clarification, Linien is basically a fork of redpid, building mainly on the FPGA gateware written in migen (see gateware directory). So there is no problem in changing this other than the fact that somebody actually has to do it ;)
Continue in #324,
loop filter transfer function
Ability to change the overall gain, fi and fd corner frequency separately
One needs to set P, I and D then get a set of kp=P/4096, ki=I/0.1s and kd=D / (2^6 * 125e6). However, in PID tuning use case, people usually want to change kp, fi, fd separately, corner frequencies fi = 4096/PI10 Hz, fd = P/4096/D2^6125e6 Hz. But if you change P, fi and fp will change. Better to provide an option for user to input L(f) = kp * (1 + fi / f + fd * f), kp, fi, fd are free parameters.
Limited corner frequencies
If I set P = 100, the lowest fi = 410Hz because minimum I = 1, the lowest fd = 23.8kHz because max D = 8191. But this might be a hardware limit which is hard to improve. We can find external gain to bypass it.
Add a D gain limit
See my measurement of linien transfer function on a VNA below. The D gain goes up all the way to >18MHz then it drops. But due to the latency, D gain cannot provide phase lead >2MHz, extra gain only makes the loop unstable (in my lock, I observe 500kHz oscillation). It is better to have a D gain limit that can be tuned.
We can add external filters to do this. This is just a plus.
I gain limit can help with 1. some actuators like diode current in ECDL cannot take too much gain. 2. limited gain at DC makes the offset compensation easier to tune. See the red line in the above figure.
We can add external filters to do this. This is just a plus.
I know this part might be too much for a free project and they might be hard because it depends on redpid (?). I just want to provide some ideas according to my locking experience to make the project more powerful. :)
To be continued...
The text was updated successfully, but these errors were encountered: