average mode in ADC build 1

[kylinzzx]

Hi,

We are testing our ADC board (Build 1) these days, and get some problems.
Our DAC is GHzDAC with Build 8. The verrsion of the fpga server is 2904888,
The circuit diagram shows in the picture and the testing code fpgaTest

1. After ghz_fpgas.adc_bringup, the data would come in fine or at least one channel would have random value (see the picture)
   
   By running adc_bringup for a couple of times, the random value may dispear, and the adc may work well until next adc_bringup.
   I've checked the twiki page, and find similar issue. But our ADC board is not the prototype board according to the method to distinguish prototype from v1.0 written in the twiki page.
   We want to know if board v1.0 also gets this issue and how we can get rid of it.
2. In our setup, the ADC should saturate when the DAC Amplitude is about 0.5, (amp=1.0 represents the maximal output of the DAC)
   but we find the data is overflow when DAC amplitude is about 0.25, shown in the picture ( dac amp=0.4 is chosen in the picture) .
   When the dac amplitude is about 0.5, ADC board saturates, and we find the LED3/LED4 ON, indicating that I/Q is out of range (we choose dac amp=0.65 here).
   Function average(sample, fpga, 30) is used.
   
   The data overflow when amp=0.4 is strange since I/Q is not out of range according to the LED3/LED4. And it seems that the integer is in 17bit not 16bit.
3. The data come from ADC does not increase when reps gets larger as the documentation
   GHzADv7 writes.
   The function we used is sumCheck(sample, fpga, repetitions=[30,120]), and the data we taken is
   shown below.
   

Please help us to solve these problems
Thank you.