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Not an issue, need some help #8

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SscSPs opened this issue Jul 22, 2017 · 2 comments
Open

Not an issue, need some help #8

SscSPs opened this issue Jul 22, 2017 · 2 comments

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@SscSPs
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SscSPs commented Jul 22, 2017

Sorry if it's not okay for making this post here, but I don't know where I can talk to you.
I need some help with building a kernel.
I have a 3.4 kernel and I am having sepolicy related issues.
Can you help me with it?

Here is the last_kmsg: https://hastebin.com/kahijigiho.vbs
And here is my kernel: https://github.com/samsunggalaxytab3/android_kernel_samsung_lt02/

Can you please help me with this? Or tell me anyone who can?
@kerneltoast
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kerneltoast commented Jul 22, 2017 via email

@SscSPs
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SscSPs commented Jul 22, 2017

Thanks for the reply, but I fixed it already, I guess, now I have other Issue.
I used http://seandroid-list.tycho.nsa.narkive.com/D3qnO4XY/restorecon-init-fail-in-the-init-cpp-file as a reference and picked the code(couldn't find the commit) and applied it in my kernel,
SamsungGalaxyTab3/android_kernel_samsung_lt02@d1180b4 this is the commit that fixed that particular issue.

Now, new issue is here, I think this is normal issues that can be fixed in sepolicies defined in the device tree? or some other things?
https://hastebin.com/ovewogamih.vbs
If you can, please take a look and if you see something that you know how to fix, please tell me.
I am just a noob, trying to learn the hard stuff by undertaking a old-ass device's development. :)

bladehawkz pushed a commit to bladehawkz/Bladehawkz-Kernel that referenced this issue Jan 16, 2018
ARM: 7493/1: use generic unaligned.h
9c7d128 
This moves ARM over to the asm-generic/unaligned.h header. This has the
benefit of better code generated especially for ARMv7 on gcc 4.7+
compilers.

As Arnd Bergmann, points out: The asm-generic version uses the "struct"
version for native-endian unaligned access and the "byteshift" version
for the opposite endianess. The current ARM version however uses the
"byteshift" implementation for both.

Thanks to Nicolas Pitre for the excellent analysis:

Test case:

int foo (int *x) { return get_unaligned(x); }
long long bar (long long *x) { return get_unaligned(x); }

With the current ARM version:

foo:
	ldrb	r3, [r0, kerneltoast#2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, kerneltoast#1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	r3, r3, asl #16	@ tmp154, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r0, [r0, kerneltoast#3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	r3, r3, r1, asl kerneltoast#8	@, tmp155, tmp154, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r3, r2	@ tmp157, tmp155, MEM[(const u8 *)x_1(D)]
	orr	r0, r3, r0, asl #24	@,, tmp157, MEM[(const u8 *)x_1(D) + 3B],
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	mov	r2, #0	@ tmp184,
	ldrb	r5, [r0, kerneltoast#6]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 6B], MEM[(const u8 *)x_1(D) + 6B]
	ldrb	r4, [r0, kerneltoast#5]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 5B], MEM[(const u8 *)x_1(D) + 5B]
	ldrb	ip, [r0, kerneltoast#2]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 2B], MEM[(const u8 *)x_1(D) + 2B]
	ldrb	r1, [r0, kerneltoast#4]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 4B], MEM[(const u8 *)x_1(D) + 4B]
	mov	r5, r5, asl #16	@ tmp175, MEM[(const u8 *)x_1(D) + 6B],
	ldrb	r7, [r0, kerneltoast#1]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 1B], MEM[(const u8 *)x_1(D) + 1B]
	orr	r5, r5, r4, asl kerneltoast#8	@, tmp176, tmp175, MEM[(const u8 *)x_1(D) + 5B],
	ldrb	r6, [r0, kerneltoast#7]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 7B], MEM[(const u8 *)x_1(D) + 7B]
	orr	r5, r5, r1	@ tmp178, tmp176, MEM[(const u8 *)x_1(D) + 4B]
	ldrb	r4, [r0, #0]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D)], MEM[(const u8 *)x_1(D)]
	mov	ip, ip, asl #16	@ tmp188, MEM[(const u8 *)x_1(D) + 2B],
	ldrb	r1, [r0, kerneltoast#3]	@ zero_extendqisi2	@ MEM[(const u8 *)x_1(D) + 3B], MEM[(const u8 *)x_1(D) + 3B]
	orr	ip, ip, r7, asl kerneltoast#8	@, tmp189, tmp188, MEM[(const u8 *)x_1(D) + 1B],
	orr	r3, r5, r6, asl #24	@,, tmp178, MEM[(const u8 *)x_1(D) + 7B],
	orr	ip, ip, r4	@ tmp191, tmp189, MEM[(const u8 *)x_1(D)]
	orr	ip, ip, r1, asl #24	@, tmp194, tmp191, MEM[(const u8 *)x_1(D) + 3B],
	mov	r1, r3	@,
	orr	r0, r2, ip	@ tmp171, tmp184, tmp194
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

In both cases the code is slightly suboptimal.  One may wonder why
wasting r2 with the constant 0 in the second case for example.  And all
the mov's could be folded in subsequent orr's, etc.

Now with the asm-generic version:

foo:
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	bx	lr	@

bar:
	mov	r3, r0	@ x, x
	ldr	r0, [r0, #0]	@ unaligned	@,* x
	ldr	r1, [r3, kerneltoast#4]	@ unaligned	@,
	bx	lr	@

This is way better of course, but only because this was compiled for
ARMv7. In this case the compiler knows that the hardware can do
unaligned word access.  This isn't that obvious for foo(), but if we
remove the get_unaligned() from bar as follows:

long long bar (long long *x) {return *x; }

then the resulting code is:

bar:
	ldmia	r0, {r0, r1}	@ x,,
	bx	lr	@

So this proves that the presumed aligned vs unaligned cases does have
influence on the instructions the compiler may use and that the above
unaligned code results are not just an accident.

Still... this isn't fully conclusive without at least looking at the
resulting assembly fron a pre ARMv6 compilation.  Let's see with an
ARMv5 target:

foo:
	ldrb	r3, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r1, [r0, kerneltoast#1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r2, [r0, kerneltoast#2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r0, [r0, kerneltoast#3]	@ zero_extendqisi2	@ tmp146,
	orr	r3, r3, r1, asl kerneltoast#8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r2, asl #16	@, tmp145, tmp142, tmp143,
	orr	r0, r3, r0, asl #24	@,, tmp145, tmp146,
	bx	lr	@

bar:
	stmfd	sp!, {r4, r5, r6, r7}	@,
	ldrb	r2, [r0, #0]	@ zero_extendqisi2	@ tmp139,* x
	ldrb	r7, [r0, kerneltoast#1]	@ zero_extendqisi2	@ tmp140,
	ldrb	r3, [r0, kerneltoast#4]	@ zero_extendqisi2	@ tmp149,
	ldrb	r6, [r0, kerneltoast#5]	@ zero_extendqisi2	@ tmp150,
	ldrb	r5, [r0, kerneltoast#2]	@ zero_extendqisi2	@ tmp143,
	ldrb	r4, [r0, kerneltoast#6]	@ zero_extendqisi2	@ tmp153,
	ldrb	r1, [r0, kerneltoast#7]	@ zero_extendqisi2	@ tmp156,
	ldrb	ip, [r0, kerneltoast#3]	@ zero_extendqisi2	@ tmp146,
	orr	r2, r2, r7, asl kerneltoast#8	@, tmp142, tmp139, tmp140,
	orr	r3, r3, r6, asl kerneltoast#8	@, tmp152, tmp149, tmp150,
	orr	r2, r2, r5, asl #16	@, tmp145, tmp142, tmp143,
	orr	r3, r3, r4, asl #16	@, tmp155, tmp152, tmp153,
	orr	r0, r2, ip, asl #24	@,, tmp145, tmp146,
	orr	r1, r3, r1, asl #24	@,, tmp155, tmp156,
	ldmfd	sp!, {r4, r5, r6, r7}
	bx	lr

Compared to the initial results, this is really nicely optimized and I
couldn't do much better if I were to hand code it myself.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Pranav Vashi <neobuddy89@gmail.com>
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@kerneltoast @SscSPs