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Hi, I'm currently writing (well ... rewriting) a driver for a custom USB core used in several FPGA project and that's also being taped out in a ASIC soon ( https://github.com/no2fpga/no2usb ). The hardware has support for dual packet buffer for the EPs and I'm wondering if there would be any ill-effect in reporting the transfer as being complete when I submitted the packets to the hardware, or if I have to wait for the hardware to report completion of the TX before doing so. Cheers, Sylvain |
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Replies: 1 comment 8 replies
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I think you should trigger the interrupt after packet complete i.e the data and CRC has been checked and/or ACK is being returned. Should something bad happened such as bad data toggle, incorrect checksum or more often STALLED response from host, it should report back to software. Depending on the class driver (stall may has different meaning for each class), tinyusb will decide to re-submit or abort the transfer. |
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I think you should trigger the interrupt after packet complete i.e the data and CRC has been checked and/or ACK is being returned. Should something bad happened such as bad data toggle, incorrect checksum or more often STALLED response from host, it should report back to software. Depending on the class driver (stall may has different meaning for each class), tinyusb will decide to re-submit or abort the transfer.