[enhancement] Support 1R/1W RAM Models (with RAM rewriting)

[rw1nkler]

What's hard to do? (limit 100 words)

There is currently no ROM Model available in DSLX. Although a RamModel (1R1W RAM) can be used as a substitute in tests, it is impossible to use RAM rewriting for a proc that uses only the read-port of the RamModel. Also, we think that having a single 1W RAM could be beneficial if XLS is used to generate a module responsible for filling 1R1W RAM with data, while the read port is used by another part of the design (outside XLS)

Current best alternative workaround (limit 100 words)

Use the 1R1W RAM model with fake accesses to the unused ports.

send_if(tok, ram_rd_req, false, ...)
recv_if(tok, ram_rd_resp, false, ...)
or
send_if(tok, ram_wr_req, false, ...)
recv_if(tok, ram_wr_resp, false, ...)

Then, leave the unused ports unconnected in the generated Verilog code.

Your view of the "best case XLS enhancement" (limit 100 words)

The 1R and 1W RAM models could be available in XLS, and the RAM rewriting step could allow for rewriting their read/write port

[cunninghamsandwich]

Thanks for reporting! As discussed in our April enhancement proposal review meeting: we've added this to our Usability Sprint.