[Bug] --vendor-library=NAME ha no effect during synthesys
#2523
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How did you instantiate |
@tgingold My VHDL file content, which I want to synthesize, is: -------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : PcieBlock_x1_pcie_bram_7x.vhd
-- Version : 3.3
-- Description : single bram wrapper for the mb pcie block
-- The bram A port is the write port
-- the B port is the read port
--
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library unimacro;
use unimacro.vcomponents.all;
entity PcieBlock_x1_pcie_bram_7x is
generic(
LINK_CAP_MAX_LINK_SPEED : INTEGER := 1; -- PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
LINK_CAP_MAX_LINK_WIDTH : INTEGER := 8; -- PCIe Link Width : 1 / 2 / 4 / 8
IMPL_TARGET : STRING := "HARD"; -- the implementation target : HARD, SOFT
DOB_REG : INTEGER := 0; -- 1 - use the output register;
-- 0 - don't use the output register
WIDTH : INTEGER := 0 -- supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
-- 72 - uses RAMB36SDP
);
port (
user_clk_i : in std_logic; -- user clock
reset_i : in std_logic; -- bram reset
wen_i : in std_logic; -- write enable
waddr_i : in std_logic_vector(12 downto 0); -- write address
wdata_i : in std_logic_vector(WIDTH - 1 downto 0); -- write data
ren_i : in std_logic; -- read enable
rce_i : in std_logic; -- output register clock enable
raddr_i : in std_logic_vector(12 downto 0); -- read address
rdata_o : out std_logic_vector(WIDTH - 1 downto 0) -- read data
);
end PcieBlock_x1_pcie_bram_7x;
architecture v7_pcie of PcieBlock_x1_pcie_bram_7x is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of v7_pcie : architecture is "yes";
-- map the address bits
function msb_addr (
constant wdt : integer)
return integer is
variable addr_msb : integer := 8;
begin -- msb_addr
if (wdt = 4) then
addr_msb := 12;
elsif (wdt = 9) then
addr_msb := 11;
elsif (wdt = 18) then
addr_msb := 10;
elsif (wdt = 36) then
addr_msb := 9;
else
addr_msb := 8;
end if;
return addr_msb;
end msb_addr;
constant ADDR_MSB : integer := msb_addr(WIDTH);
-- set the width of the tied off low address bits
function alb (
constant wdt : integer)
return integer is
variable addr_lo_bit : integer := 8;
begin -- alb
if (wdt = 4) then
addr_lo_bit := 2;
elsif (wdt = 9) then
addr_lo_bit := 3;
elsif (wdt = 18) then
addr_lo_bit := 4;
elsif (wdt = 36) then
addr_lo_bit := 5;
else
addr_lo_bit := 0; -- for WIDTH 72 use RAMB36SDP
end if;
return addr_lo_bit;
end alb;
constant ADDR_LO_BITS : integer := alb(WIDTH);
-- map the data bits
function msb_d (
constant wdt : integer)
return integer is
variable dmsb : integer := 8;
begin -- msb_d
if (wdt = 4) then
dmsb := 3;
elsif (wdt = 9) then
dmsb := 7;
elsif (wdt = 18) then
dmsb := 15;
elsif (wdt = 36) then
dmsb := 31;
else
dmsb := 63;
end if;
return dmsb;
end msb_d;
constant D_MSB : integer := msb_d(WIDTH);
-- map the data parity bits
constant DP_LSB : integer := D_MSB + 1;
function msb_dp (
constant wdt : integer)
return integer is
variable dpmsb : integer := 8;
begin -- msb_dp
if (wdt = 4) then
dpmsb := 4;
elsif (wdt = 9) then
dpmsb := 8;
elsif (wdt = 18) then
dpmsb := 17;
elsif (wdt = 36) then
dpmsb := 35;
else
dpmsb := 71;
end if;
return dpmsb;
end msb_dp;
function pad_val (
in_vec : std_logic_vector;
range_hi : integer;
range_lo : integer;
pad : std_logic;
op_len : integer)
return std_logic_vector is
variable ret : std_logic_vector(op_len-1 downto 0) := (others => '0');
begin -- pad_val
for i in 0 to op_len-1 loop
if ((i >= range_lo) and (i <= range_hi)) then
ret(i) := in_vec(i - range_lo);
else
ret(i) := pad;
end if;
end loop; -- i
return ret;
end pad_val;
function device_val (
impl_target : string)
return string is
begin -- dev
if (impl_target = "HARD") then
return "7SERIES";
else
return "VIRTEX6";
end if;
end device_val;
function get_write_mode (
link_width : integer;
WIDTH : integer;
link_speed : integer)
return string is
begin -- wr_mode
if ((WIDTH = 72) and (not((link_width =8) and (link_speed = 2)))) then
return "WRITE_FIRST";
elsif ((link_width =8) and (link_speed = 2)) then
return "WRITE_FIRST";
else
return "NO_CHANGE";
end if;
end get_write_mode;
function get_we_width (
DEVICE : string;
WIDTH : integer)
return integer is
begin -- wr_mode
if ((DEVICE = "VIRTEX5") or (DEVICE = "VIRTEX6") or (DEVICE = "7SERIES")) then
if (WIDTH <= 9) then
return 1;
elsif (WIDTH > 9 and WIDTH <= 18) then
return 2;
elsif (WIDTH > 18 and WIDTH <= 36) then
return 4;
elsif (WIDTH > 36 and WIDTH <= 72) then
return 8;
else
return 8;
end if;
else
return 8;
end if;
end get_we_width;
constant DP_MSB : integer := msb_dp(WIDTH);
constant DPW : integer := DP_MSB - DP_LSB + 1;
constant WRITE_MODE : string := get_write_mode(LINK_CAP_MAX_LINK_WIDTH,WIDTH,LINK_CAP_MAX_LINK_SPEED);
constant BRAM_SIZE : string := "36Kb";
constant DEVICE : string := device_val(IMPL_TARGET);
constant WE_WIDTH : integer := get_we_width(DEVICE,WIDTH);
signal DIB_dummy : std_logic_vector ((WIDTH-1) downto 0);
signal WE_dummy_gnd : std_logic_vector ((WE_WIDTH-1) downto 0);
signal WE_dummy_vcc : std_logic_vector ((WE_WIDTH-1) downto 0);
signal rdata_o_dummy : std_logic_vector (WIDTH-1 downto 0);
begin
-- Tie off dummy vectors
DIB_dummy <= (others => '0');
WE_dummy_gnd <= (others => '0');
WE_dummy_vcc <= (others => '1');
--synthesis translate_off
process
begin
--$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
-- $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case WIDTH is
when 4 | 9 | 18 | 36 | 72 =>
when others => -- case (WIDTH)
-- $display("[%t] %m Error WIDTH %0d not supported", now, to_stdlogic(WIDTH));
-- $finish();
end case;
wait;
end process;
--synthesis translate_on
use_sdp : if (((LINK_CAP_MAX_LINK_WIDTH = "001000") and (LINK_CAP_MAX_LINK_SPEED = "0010")) or ( WIDTH = 72)) generate
-- v6pcie2 <= (others => wen_i);
-- rdata_o_v6pcie0 <= v6pcie16((DP_MSB - DP_LSB) downto 0) & v6pcie15(D_MSB downto 0);
-- use RAMB36SDP if the width is 72 or X8GEN2
ramb36sdp : BRAM_SDP_MACRO
generic map (
DEVICE => DEVICE,
BRAM_SIZE => BRAM_SIZE,
DO_REG => DOB_REG,
READ_WIDTH => WIDTH,
WRITE_WIDTH => WIDTH,
WRITE_MODE => WRITE_MODE
)
port map (
DO => rdata_o(WIDTH-1 downto 0),
DI => wdata_i(WIDTH-1 downto 0),
RDADDR => raddr_i(ADDR_MSB downto 0),
RDCLK => user_clk_i,
RDEN => ren_i,
REGCE => rce_i,
RST => reset_i,
WE => WE_dummy_vcc,
WRADDR => waddr_i(ADDR_MSB downto 0),
WRCLK => user_clk_i,
WREN => wen_i
);
-- use RAMB36's if the width is 4, 9, 18, or 36
end generate;
use_tdp : if (( WIDTH <= 36) and (not((LINK_CAP_MAX_LINK_WIDTH = "001000") and (LINK_CAP_MAX_LINK_SPEED = "0010")))) generate
-- use RAMB36SDP if the width is 72 or X8GEN2
ramb36 : BRAM_TDP_MACRO
generic map (
DEVICE => DEVICE,
BRAM_SIZE => BRAM_SIZE,
DOA_REG => 0,
DOB_REG => DOB_REG,
READ_WIDTH_A => WIDTH,
READ_WIDTH_B => WIDTH,
WRITE_WIDTH_A => WIDTH,
WRITE_WIDTH_B => WIDTH,
WRITE_MODE_A => WRITE_MODE
)
port map (
DOA => rdata_o_dummy(WIDTH-1 downto 0),
DOB => rdata_o(WIDTH-1 downto 0),
ADDRA => waddr_i(ADDR_MSB downto 0),
ADDRB => raddr_i(ADDR_MSB downto 0),
CLKA => user_clk_i,
CLKB => user_clk_i,
DIA => wdata_i(WIDTH-1 downto 0),
DIB => DIB_dummy,
ENA => wen_i,
ENB => ren_i,
REGCEA => '0',
REGCEB => rce_i,
RSTA => reset_i,
RSTB => reset_i,
WEA => WE_dummy_vcc,
WEB => WE_dummy_gnd
);
end generate;
end v7_pcie;The commands I run, are:
The errors and warnings generated are: The error is at the last log line. Also, it seems this -----------------------------------------
----------- FPGA Globals --------------
-----------------------------------------
signal GSR : std_logic := '0';This I wonder what I'm doing wrong, and how these global signals from Xilinx can be managed, in the synthesis phase. Also, all of those Xilinx primitives should be defined as black boxes when synthesizing, or it would be still possibile to synthesize them someway? |
|
You are running two commands: ghdl make and ghdl synth. Which one generates the error ? I suppose this is the first one (ghdl make). And, these primitives should be defined as black box (except maybe unimacros) |
|
This is what I did, we consider the source file I provided above as the input file.
|
|
Hello @tgingold, just wanted to ask if these steps are enough or if you need more information to replicate the issue. If yes, I'll be more than willing to provide them 👍. |
|
As I don't have vivado installed on my machine, it would be nice if you could create a standalone reproducer. |
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Description
--vendor-library=NAMEis a synth option which allows to replace any unit fromLIB_NAMEwith a black box during synthesys:https://ghdl.github.io/ghdl/using/Synthesis.html
I'm using that option as an argument to the synthesys:
ghdl make -Wall -fsynopsys -fexplicit --workdir=ghdl_lib -PC:/GHDL/lib/ghdl/vendors/altera -PC:/GHDL/lib/ghdl/vendors/xilinx-vivado --std=08 -frelaxed Top_ENT && MKDIR ghdl_out & ghdl synth -Wall -fsynopsys -fexplicit --workdir=ghdl_lib -PC:/GHDL/lib/ghdl/vendors/altera -PC:/GHDL/lib/ghdl/vendors/xilinx-vivado --std=08 -frelaxed --out=verilog --latches --vendor-library=unisim --vendor-library=altera_mf Top_ENTProblem is that
ghdlreports an error,signal assignment not allowed herefor a Xilinx source file:C:\Xilinx\Vivado\2020.2\data\vhdl\src\unisims\primitive\IBUFDS.vhdof an entity which probably gets instantiated in one of my source files, which belongs to the
unisimlibrary.Also, all of the source files defined in the
altera_mflibrary get parsed and analyzed, even if the--vendor-libraryargument is applied:Expected behaviour
I would expect
--vendor-library=unisimto skip theIBUFDSentity analysis defined in the Xilinxunisimlibrary, so that the error is not generated during synthesys (IBUFDSinstances would be considered as black boxes?).How to reproduce?
Context
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