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vivado_2504.backup.log
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vivado_2504.backup.log
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#-----------------------------------------------------------
# Vivado v2019.2 (64-bit)
# SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
# IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019
# Start of session at: Mon Mar 2 09:53:33 2020
# Process ID: 2504
# Current directory: C:/Users/Shantanu Shinde/Desktop/Shantanu/TIFR/Fine Counter Codes/Hybrid_Counter
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19864 C:\Users\Shantanu Shinde\Desktop\Shantanu\TIFR\Fine Counter Codes\Hybrid_Counter\Hybrid_Counter.xpr
# Log file: C:/Users/Shantanu Shinde/Desktop/Shantanu/TIFR/Fine Counter Codes/Hybrid_Counter/vivado.log
# Journal file: C:/Users/Shantanu Shinde/Desktop/Shantanu/TIFR/Fine Counter Codes/Hybrid_Counter\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {C:/Users/Shantanu Shinde/Desktop/Shantanu/TIFR/Fine Counter Codes/Hybrid_Counter/Hybrid_Counter.xpr}
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
INFO: [Common 17-344] 'open_project' was cancelled
open_project {C:/Users/Shantanu Shinde/Desktop/Shantanu/TIFR/Fine Counter Codes/Hybrid_Counter/Hybrid_Counter.xpr}
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2019.2/data/ip'.
open_project: Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 859.051 ; gain = 62.145
update_compile_order -fileset sources_1
open_hw_manager
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx hw_server v2019.2
**** Build date : Nov 6 2019 at 22:12:23
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3417] Launching cs_server...
INFO: [Labtools 27-2221] Launch Output:
****** Xilinx cs_server v2019.2.0
**** Build date : Nov 07 2019-10:58:22
** Copyright 2017-2019 Xilinx, Inc. All Rights Reserved.
connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 888.398 ; gain = 18.266
disconnect_hw_server: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2132.785 ; gain = 1243.473
connect_hw_server -url localhost:3121 -allow_non_jtag
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-3415] Connecting to cs_server url TCP:localhost:3042
INFO: [Labtools 27-3414] Connected to existing cs_server.
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/210292ABF811A]
set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/210292ABF811A]
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210292ABF811A
current_hw_device [get_hw_devices xc7a100t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a100t_0] 0]
INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
close_hw_manager
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
exit
INFO: [Common 17-206] Exiting Vivado at Tue Mar 3 17:39:07 2020...