{"payload":{"header_redesign_enabled":false,"results":[{"id":"2193651","archived":false,"color":"#b2b7f8","followers":38,"has_funding_file":false,"hl_name":"dwelch67/lsasim","hl_trunc_description":"Educational load/store instruction set architecture processor simulator","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":2193651,"name":"lsasim","owner_id":385964,"owner_login":"dwelch67","updated_at":"2013-03-20T19:28:13.000Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":49,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Adwelch67%252Flsasim%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/dwelch67/lsasim/star":{"post":"qnmrWaHqe8WDiUnpnX4lvxmVjLLozI-SBnnJVydWiG2ICfB8TyweS-KQsLthHUz-hg1np-0-uwsScpYabhoImA"},"/dwelch67/lsasim/unstar":{"post":"AY9xB0dC6SCokrBlpr5SfQn4WFRlXs2ln9jpgPFJEEL7Mk4ilMCs94j7eMwDh5AsOafU5lctqADXLwqjWh9HgQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"65AryTFmON0GN--Pq3C9RzpAouwKllg8Bs6rKVqZe-oluLabZcNqf8ZFoggkoXBxLMJxa-mMkzr17kr1dDkkQg"}}},"title":"Repository search results"}