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ebsp_fast.ldf
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ebsp_fast.ldf
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/*
fast.ldf
Copyright (C) 2012 Adapteva, Inc.
Contributed by Yaniv Sapir <yaniv@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
/* Default linker script, for regular executables */
OUTPUT_FORMAT("elf32-epiphany", "elf32-epiphany", "elf32-epiphany")
OUTPUT_ARCH(epiphany)
ENTRY(_start)
PROVIDE (___bss_start = __bss_start);
/* BSP specific */
__PROG_SIZE_FOR_CORE_ = 1M;
__HEAP_SIZE_FOR_CORE_ = 512K;
__HALF_BANK_SIZE_ = 4K;
__NUM_ROWS_IN_CHIP_ = 4;
__NUM_COLS_IN_CHIP_ = 4;
__FIRST_CORE_ROW_ = 32;
__FIRST_CORE_COL_ = 8;
__CORE_ROW_ = DEFINED(__CORE_ROW_) ? __CORE_ROW_ : __FIRST_CORE_ROW_;
__CORE_COL_ = DEFINED(__CORE_COL_) ? __CORE_COL_ : __FIRST_CORE_COL_;
/* generic don't touch */
/* used to calculate the slice address in the external memory */
__CORE_NUM_ = (__CORE_ROW_ - __FIRST_CORE_ROW_) * __NUM_COLS_IN_CHIP_ + (__CORE_COL_ - __FIRST_CORE_COL_);
__SHARED_DRAM_ = 0x8e000000;
MEMORY
{
EXTERNAL_DRAM_0 (WXAI) : ORIGIN = 0x8e000000, LENGTH = 0x01000000 /* .text, data, rodata, bss and .stack */
EXTERNAL_DRAM_1 (WXAI) : ORIGIN = 0x8f000000, LENGTH = 0x01000000 /* .heap */
/* run time lib and crt0 */
IVT_RAM (WXAI) : ORIGIN = 0, LENGTH = 0x28
/* user program, continuous placement */
WORKGROUP_RAM (WXAI) : ORIGIN = LENGTH(IVT_RAM), LENGTH = 0x100 - LENGTH(IVT_RAM)
/* user program, continuous placement */
INTERNAL_RAM (WXAI) : ORIGIN = LENGTH(IVT_RAM) + LENGTH(WORKGROUP_RAM), LENGTH = 32K - LENGTH(IVT_RAM) - LENGTH(WORKGROUP_RAM)
/* user program, per bank usage */
BANK0_SRAM (WXAI) : ORIGIN = LENGTH(IVT_RAM) + LENGTH(WORKGROUP_RAM), LENGTH = 8K - LENGTH(IVT_RAM) - LENGTH(WORKGROUP_RAM)
BANK1_SRAM (WXAI) : ORIGIN = 0x2000, LENGTH = 8K
BANK2_SRAM (WXAI) : ORIGIN = 0x4000, LENGTH = 8K
BANK3_SRAM (WXAI) : ORIGIN = 0x6000, LENGTH = 8K
/* system registers */
MMR (WAI) : ORIGIN = 0xF0000, LENGTH = 32K
/* multicore (global) space */
CORE_0x20_0x08_INTERNAL_RAM : ORIGIN = 0x80800000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x20_0x09_INTERNAL_RAM : ORIGIN = 0x80900000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x20_0x0a_INTERNAL_RAM : ORIGIN = 0x80a00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x20_0x0b_INTERNAL_RAM : ORIGIN = 0x80b00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x21_0x08_INTERNAL_RAM : ORIGIN = 0x84800000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x21_0x09_INTERNAL_RAM : ORIGIN = 0x84900000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x21_0x0a_INTERNAL_RAM : ORIGIN = 0x84a00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x21_0x0b_INTERNAL_RAM : ORIGIN = 0x84b00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x22_0x08_INTERNAL_RAM : ORIGIN = 0x88800000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x22_0x09_INTERNAL_RAM : ORIGIN = 0x88900000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x22_0x0a_INTERNAL_RAM : ORIGIN = 0x88a00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x22_0x0b_INTERNAL_RAM : ORIGIN = 0x88b00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x23_0x08_INTERNAL_RAM : ORIGIN = 0x8c800000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x23_0x09_INTERNAL_RAM : ORIGIN = 0x8c900000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x23_0x0a_INTERNAL_RAM : ORIGIN = 0x8ca00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
CORE_0x23_0x0b_INTERNAL_RAM : ORIGIN = 0x8cb00000 + LENGTH(IVT_RAM), LENGTH = 32K - LENGTH(IVT_RAM)
}
SECTIONS
{
ivt_reset 0x00 : {*.o(IVT_RESET)} > IVT_RAM
ivt_software_exception 0x04 : {*.o(ivt_entry_software_exception)} > IVT_RAM
ivt_page_miss 0x08 : {*.o(ivt_entry_page_miss)} > IVT_RAM
ivt_timer0 0x0c : {*.o(ivt_entry_timer0)} > IVT_RAM
ivt_timer1 0x10 : {*.o(ivt_entry_timer1)} > IVT_RAM
ivt_message 0x14 : {*.o(ivt_entry_message)} > IVT_RAM
ivt_dma0 0x18 : {*.o(ivt_entry_dma0)} > IVT_RAM
ivt_dma1 0x1c : {*.o(ivt_entry_dma1)} > IVT_RAM
ivt_wand 0x20 : {*.o(ivt_entry_wand)} > IVT_RAM
ivt_user 0x24 : {*.o(ivt_entry_user)} > IVT_RAM
/* section filled in by loader */
workgroup_cfg 0x28 :
{
*(workgroup_cfg)
ASSERT(. <= 0x28, "workgroup_cfg section overflow");
. = 0x28; /* force allocation */
} > WORKGROUP_RAM /* 28 2c 30 34 38 3c 40 44 48 (4c) */
/* section filled in by loader */
ext_mem_cfg 0x50 :
{
*(ext_mem_cfg);
ASSERT(. <= 0x8, "ext_mem_cfg section overflow");
. = 0x8; /* force allocation */
} > WORKGROUP_RAM /* 50 54 */
/* section filled in by loader */
loader_cfg 0x58 :
{
*(loader_cfg);
ASSERT(. <= 0x10, "loader_cfg section overflow");
. = 0x10; /* force allocation */
} > WORKGROUP_RAM /* 58 5C 60 64 */
/* place the ISR handlers after workgroup-configuration */
.reserved_crt0 ORIGIN(IVT_RAM) + LENGTH(IVT_RAM) + LENGTH(WORKGROUP_RAM) : {*.o(RESERVED_CRT0) *.o(reserved_crt0)} > INTERNAL_RAM
. = ADDR(.reserved_crt0) + SIZEOF(.reserved_crt0);
.data_bank0 . : {*.o(.data_bank0)} > BANK0_SRAM
. = ADDR(.data_bank0) + SIZEOF(.data_bank0);
.text_bank0 . : {*.o(.text_bank0)} > BANK0_SRAM
.data_bank1 : {*.o(.data_bank1)} > BANK1_SRAM
.text_bank1 : {*.o(.text_bank1)} > BANK1_SRAM
.data_bank2 : {*.o(.data_bank2)} > BANK2_SRAM
.text_bank2 : {*.o(.text_bank2)} > BANK2_SRAM
.data_bank3 : {*.o(.data_bank3)} > BANK3_SRAM
.text_bank3 : {*.o(.text_bank3)} > BANK3_SRAM
.code_dram : {*.o(code_dram) *.o(.code_dram) } > EXTERNAL_DRAM_0
.shared_dram : {*.o(shared_dram) *.o(.shared_dram)} > EXTERNAL_DRAM_1
.heap_dram ORIGIN(EXTERNAL_DRAM_1) + LENGTH(EXTERNAL_DRAM_1) - __HEAP_SIZE_FOR_CORE_ * __NUM_ROWS_IN_CHIP_ * __NUM_COLS_IN_CHIP_ : {*.o(heap_dram) *.o(.heap_dram)} > EXTERNAL_DRAM_1
/* the newlib (libc and libm) library is mapped to the dedicated section */
/* create offset with location counter */
. = (ORIGIN(EXTERNAL_DRAM_0) + __PROG_SIZE_FOR_CORE_ * __CORE_NUM_);
NEW_LIB_RO . : {lib_a-*.o(.text .rodata) *.o(libgloss_epiphany) } > EXTERNAL_DRAM_0
NEW_LIB_WR . : {lib_a-*.o(.data) } > EXTERNAL_DRAM_0
GNU_C_BUILTIN_LIB_RO . :
{
*mulsi3.o(.text .rodata) *modsi3.o(.text .rodata)
*divsi3.o(.text .rodata) *udivsi3.o(.text .rodata)
*umodsi3.o(.text .rodata) _*.o(.text .rodata)
} > EXTERNAL_DRAM_0
EBSP_TEXT . : { } > EXTERNAL_DRAM_0
EBSP_RO . : { } > EXTERNAL_DRAM_0
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.rela.plt :
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.init ADDR(.data_bank0) + SIZEOF(.data_bank0) :
{
KEEP (*(.init))
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/* .gnu.warning sections are handled specially by elf32.em. */
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} > INTERNAL_RAM =0
.fini :
{
KEEP (*(.fini))
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PROVIDE (__etext = .);
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/* These sections are generated by the Sun/Oracle C++ compiler. */
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}> INTERNAL_RAM
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The .ctor section from the crtend file contains the
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KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}> INTERNAL_RAM
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{
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KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}> INTERNAL_RAM
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