{"payload":{"header_redesign_enabled":false,"results":[{"id":"30977781","archived":false,"color":"#b2b7f8","followers":221,"has_funding_file":false,"hl_name":"cliffordwolf/SimpleVOut","hl_trunc_description":"A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":30977781,"name":"SimpleVOut","owner_id":619764,"owner_login":"cliffordwolf","updated_at":"2018-11-29T06:10:42.093Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Acliffordwolf%252FSimpleVOut%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/cliffordwolf/SimpleVOut/star":{"post":"lXNaoQNPhOMwQUL8iBjgrxDWnl_cXTFx4vWZ99dzeDH-ifPQ2NkFca7l2M0Qvx6sA8bRnP_msrJ_8qXJCoUmig"},"/cliffordwolf/SimpleVOut/unstar":{"post":"54fHgM0mojYegQ7XfhP1C46MgtPSoq4zq-jcDxj2OgIpV0ufhwHNhnS4vQ8aGJ2iA4k0LvwlRXzKz4ZDVCwuQg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"rzfN_xzzWI3dj07b35fCJ_Zm3Z4HL6KgHRwLDOCkZDnSBEn8HU9pjXHFUAUISmx8-jYDWUhhIq79SaaX-4Awag"}}},"title":"Repository search results"}