/
common.sc
160 lines (137 loc) · 5.25 KB
/
common.sc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <liu@jiuyang.me>
import mill._
import mill.scalalib._
trait HasChisel
extends ScalaModule {
// Define these for building chisel from source
def chiselModule: Option[ScalaModule]
override def moduleDeps = super.moduleDeps ++ chiselModule
def chiselPluginJar: T[Option[PathRef]]
override def scalacOptions = T(super.scalacOptions() ++ chiselPluginJar().map(path => s"-Xplugin:${path.path}") ++ Seq("-Ymacro-annotations"))
override def scalacPluginClasspath: T[Agg[PathRef]] = T(super.scalacPluginClasspath() ++ chiselPluginJar())
// Define these for building chisel from ivy
def chiselIvy: Option[Dep]
override def ivyDeps = T(super.ivyDeps() ++ chiselIvy)
def chiselPluginIvy: Option[Dep]
override def scalacPluginIvyDeps: T[Agg[Dep]] = T(super.scalacPluginIvyDeps() ++ chiselPluginIvy.map(Agg(_)).getOrElse(Agg.empty[Dep]))
}
trait HasRVDecoderDB extends ScalaModule {
def rvdecoderdbModule: ScalaModule
def riscvOpcodesPath: T[PathRef]
def moduleDeps = super.moduleDeps ++ Seq(rvdecoderdbModule)
def riscvOpcodesTar: T[PathRef] = T {
val tmpDir = os.temp.dir()
os.makeDir(tmpDir / "unratified")
os.walk(riscvOpcodesPath().path)
.filter(f =>
f.baseName.startsWith("rv128_") ||
f.baseName.startsWith("rv64_") ||
f.baseName.startsWith("rv32_") ||
f.baseName.startsWith("rv_") ||
f.ext == "csv"
).groupBy(_.segments.contains("unratified")).map {
case (true, fs) => fs.map(os.copy.into(_, tmpDir / "unratified"))
case (false, fs) => fs.map(os.copy.into(_, tmpDir))
}
os.proc("tar", "cf", T.dest / "riscv-opcodes.tar", ".").call(tmpDir)
PathRef(T.dest)
}
override def resources: T[Seq[PathRef]] = super.resources() ++ Some(riscvOpcodesTar())
}
// Local definitions
trait T1Module
extends ScalaModule
with HasChisel
with HasRVDecoderDB {
def arithmeticModule: ScalaModule
def hardfloatModule: ScalaModule
def tilelinkModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(arithmeticModule, hardfloatModule, tilelinkModule)
}
trait ConfigGenModule
extends ScalaModule {
def t1Module: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(t1Module)
def mainargsIvy: Dep
override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
}
// T1 forked version of RocketCore
trait RocketModule
extends ScalaModule
with HasChisel
with HasRVDecoderDB {
def rocketchipModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(rocketchipModule)
}
trait EmuHelperModule
extends ScalaModule
with HasChisel
trait IPEmulatorModule
extends ScalaModule
with HasChisel {
def t1Module: ScalaModule
def emuHelperModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(t1Module, emuHelperModule)
}
trait SubsystemModule
extends ScalaModule
with HasChisel {
def t1Module: ScalaModule
def rocketModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(t1Module, rocketModule)
}
trait SubsystemEmulatorModule
extends ScalaModule
with HasChisel {
def subsystemModule: ScalaModule
def emuHelperModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(subsystemModule, emuHelperModule)
}
trait FPGAModule
extends ScalaModule
with HasChisel {
def subsystemModule: ScalaModule
def moduleDeps = super.moduleDeps ++ Seq(subsystemModule)
}
trait ElaboratorModule
extends ScalaModule
with HasChisel {
def generators: Seq[ScalaModule]
def panamaconverterModule: ScalaModule
def circtInstallPath: T[PathRef]
override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule) ++ generators
def mainargsIvy: Dep
override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
override def forkArgs: T[Seq[String]] = T(
super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
)
}
trait OMReaderLibModule
extends ScalaModule
with HasChisel {
def panamaconverterModule: ScalaModule
def circtInstallPath: T[PathRef]
override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule)
def mainargsIvy: Dep
override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
override def forkArgs: T[Seq[String]] = T(
super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
)
}
trait OMReaderModule
extends ScalaModule
with HasChisel {
def panamaconverterModule: ScalaModule
def omreaderlibModule: ScalaModule
def circtInstallPath: T[PathRef]
override def moduleDeps = super.moduleDeps ++ Seq(panamaconverterModule, omreaderlibModule)
def mainargsIvy: Dep
override def ivyDeps = T(super.ivyDeps() ++ Seq(mainargsIvy))
override def javacOptions = T(super.javacOptions() ++ Seq("--enable-preview", "--release", "21"))
override def forkArgs: T[Seq[String]] = T(
super.forkArgs() ++ Seq("--enable-native-access=ALL-UNNAMED", "--enable-preview", s"-Djava.library.path=${ circtInstallPath().path / "lib"}")
)
}