Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Introduce verilog -> cocotb simulation fud2 path #1997

Open
wants to merge 56 commits into
base: main
Choose a base branch
from

Conversation

nathanielnrn
Copy link
Contributor

@nathanielnrn nathanielnrn commented Apr 12, 2024

Introduces a path accepting .v files, presumably axi-wrapped via a fud2 foo.futil --through axi-wrapped and outputting the final contents of AXI rams simulated via cocotb.

Invocation currently has to be manually specified with --through due to the behavior of guess_state

An invocation looks like
fud2 <path to axi wrapped verilog> --from verilog-noverify --to cocotb-axi --set sim.data=<path to .data/json file>

This PR also introduces some cocotb python runners that largely looks like the xilinx cocotb harness. Those will hopefully be removed once we get the wrapper to properly interface with XRT.

Adds some runt tests as well that check the state of some AXI generation intermediate steps (including simulation output with cocotb). I think that the main changes of note besides that is this cocotb python runner mentioned above and the fud2 changes

@nathanielnrn nathanielnrn added the C: FPGA Changes for the FPGA backend label Apr 12, 2024
@nathanielnrn nathanielnrn changed the base branch from main to unique-fud2-dir June 4, 2024 20:39
Base automatically changed from unique-fud2-dir to main June 5, 2024 13:09
@nathanielnrn nathanielnrn requested a review from sampsyo June 5, 2024 13:50
@nathanielnrn
Copy link
Contributor Author

I think this is finally ready for review if someone gets the chance. I know #2084 has some implications on fud2 states, but I'd like to merge this first then migrate to Rhai if that sounds ok with @sampsyo and @sgpthomas .

@sgpthomas
Copy link
Collaborator

Yeah definitely merge this first. We're not quite ready to migrate things yet.

Copy link
Contributor

@sampsyo sampsyo left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Excellent! This all looks great! Here are just a few minor comments.

@@ -174,7 +174,7 @@ jobs:
uses: actions-rs/cargo@v1
with:
command: build
args: --all-features --manifest-path /home/calyx/Cargo.toml
args: --all --all-features --manifest-path /home/calyx/Cargo.toml
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Two tiny things: cargo build --help suggests that --all is deprecated in favor of --workspace, and just wanted to make sure that we actually do want to build everything in the workspace.

//Get yxi file from main compute program.
//TODO(nate): Can this use the `yxi` operation instead of hardcoding the build cmd calyx rule with arguments?
// Get yxi file from main compute program.
// TODO(nate): Can this use the `yxi` operation instead of hardcoding the build cmd calyx rule with arguments?
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This will probably have to wait for #1958.

// Cocotb is wants files relative to the location of the makefile.
// This is annoying to calculate on the fly, so we just copy necessary files to the build directory
e.rule("copy", "cp $in $out")?;
e.rule("make", "make DATA_PATH=$sim_data VERILOG_SOURCE=$in COCOTB_LOG_LEVEL=CRITICAL > $out")?;
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Maybe this rule should be called make-cocotb or something (instead of the more generic make)?

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
C: FPGA Changes for the FPGA backend C: fud2 experimental driver
Projects
None yet
Development

Successfully merging this pull request may close these issues.

Make calyx-py AXI wrapper cocotb testbench accept yxi interfaces and dynamic input data
4 participants