{"payload":{"header_redesign_enabled":false,"results":[{"id":"34361064","archived":false,"color":"#b2b7f8","followers":1107,"has_funding_file":false,"hl_name":"aolofsson/oh","hl_trunc_description":"Verilog library for ASIC and FPGA designers","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":34361064,"name":"oh","owner_id":2229872,"owner_login":"aolofsson","updated_at":"2024-05-08T03:14:16.944Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":74,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aaolofsson%252Foh%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/aolofsson/oh/star":{"post":"vmv94Ddf8BpBMA9qBc2rp6YJQFF4TAAKjshW8n85EqUwi1XYmnCIMFklLoTl4SM3c3Vr3LcMJwleWME36nQM9g"},"/aolofsson/oh/unstar":{"post":"T6DrsA907AEf6DmkpNtA8Rtl5bvmxn3WKnnQE75HK9XLhrpQ0wuhtN3fimi9rz8nw97DiwJg9nd7D4-NzwDhXw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"1fP8lliqdAXDT0txawstAIuW_3pNkb_6g1ouiQO6-tTCoI9Zfc0CM7XdVhHVeFKhTOFIx7YDN8N9F0BOcyr5TA"}}},"title":"Repository search results"}