{"payload":{"header_redesign_enabled":false,"results":[{"id":"26883874","archived":false,"color":"#b2b7f8","followers":1926,"has_funding_file":false,"hl_name":"alexforencich/verilog-ethernet","hl_trunc_description":"Verilog Ethernet components for FPGA implementation","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":26883874,"name":"verilog-ethernet","owner_id":508807,"owner_login":"alexforencich","updated_at":"2024-03-08T15:09:00.903Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":85,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aalexforencich%252Fverilog-ethernet%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/alexforencich/verilog-ethernet/star":{"post":"-2uJ31mVymnd0vlTCbbzac-IBkSYnWlDRs6_XCxJQJNMl7xd2PcZWJh5mJh0B8eZJUZbN-T4KH9UNwNuh69g7w"},"/alexforencich/verilog-ethernet/unstar":{"post":"oXUagWwgwoRYhNPAaLMeXW54yHXUBt6y9aBDXqchWM_h1M3yBQQROO7JaKqrFkmrsy1yt2OmmQ_-Km5tgV_-ig"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"zlmmPOkXa95sDoP3tzhPvizekaScRRxbjF16-qlIx1de1C0Gb6saKvNWQVuygYYoBgK4PMOwbyHa_EOb2jhIhQ"}}},"title":"Repository search results"}