{"payload":{"header_redesign_enabled":false,"results":[{"id":"142810315","archived":false,"color":"#b2b7f8","followers":1274,"has_funding_file":false,"hl_name":"alexforencich/verilog-axi","hl_trunc_description":"Verilog AXI components for FPGA implementation","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":142810315,"name":"verilog-axi","owner_id":508807,"owner_login":"alexforencich","updated_at":"2023-12-07T09:02:43.123Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":67,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Aalexforencich%252Fverilog-axi%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/alexforencich/verilog-axi/star":{"post":"KbHziqi56AFl_UHJSoOuKraKKmcml3BtSpM-Ib6_y25NFWCumVobREXMWBXCzyU-CDGl7mnCgna01_yF80S65w"},"/alexforencich/verilog-axi/unstar":{"post":"dtblZXB7bcSGnNzvUSSgbgDEcTy3YjFxUCV6StXrEmubxRMgzQY8bJKpCvXAm4p5_1ZRBKVojZXGGpsaGbmDIQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"qIFOPjbZ3oK8VPk6FMH1emwbg_bTJkzA2pdfmWXnd_JAbK6bbwPG3r_8gIuxmXeWOMYPa19LenQ4mVX99qMAmw"}}},"title":"Repository search results"}