Error in SRAM creation with banks #228
Comments
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me too |
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I am getting a similar error without touching the bank configuration, by just increasing the memory size of the single port tiny example to an arbitrary (?) size. Here is an example config, which fails for me. word_size = 32 # Bits
num_words = 256
human_byte_size = "{:.0f}kbytes".format((word_size * num_words)/1024/8)
# Allow byte writes
write_size = 8 # Bits # does not matter
# Single port
num_rw_ports = 1 #one rw port will provoque the error
num_r_ports = 0
num_w_ports = 0
num_spare_rows = 1
num_spare_cols = 1
ports_human = '1rw'
import os
exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())Tail, of a massive 256mb log file: The LVS process fails at verifying the netlist as signals/ networks are missing. edit: manually condensed the log even more |
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Any resolution to this issue? |
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No, we switched to DffRam for now. |
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In OpenRAM when creating an SRAM with the following configuration
It throws error:
When the num_banks is set to 1, the SRAM memory is created. Is the memory bank functionality working in OpenRAM
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