Delay/area model for basic gates

[JiacongSun]

Hi,

Inspired by the words in section 3.1.2 in H. Nichols, "Statistical Modeling of SRAMs", M.S. Thesis, UCSC, 2022.
I am interested about how OpenRAM derives the delay and area for smallest gate of basic types like NAND. Is these data directly extracted from PDK? Why not use the same strategy for DFFs, tri-gates and write drivers?

Thanks a lot if you could reply.

Regards,
Jiacong