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High Negtive Slack for three designs in OpenRoad #1589
Comments
We discourage the posting of results from commercial tools. Often the license terms prohibit this so you should be careful. I'll only respond to how you might improve the OR results in general terms. Less complex cells used in OpenROAD : this is determined by synthesis which would be yosys not OR. You can factor out the impact of synthesis by using a common post-synthesis netlist. Issues with yosys should be filed with https://github.com/YosysHQ/yosys You show "a selected timing path". Is that the most critical path in OR? "Can CTS be synthesized with multiple clock root buffers? Currently it takes only one" - there is only one root so what would be the purpose? It is hard to make progress without a test case to look at in more depth. While interesting it isn't very actionable to look at images. |
@maliberty Thanks for the heads up, I was unaware at the moment regarding the license terms. Can you please help me understand the below queries:
I have uploaded test case of Design 2 in this link: |
1 - Quite likely due to the selection of gates during techmapping in yosys/abc. Possibly due to limited gate sizes in the library. We'll have to look at the paths in detail. |
Path in gui : ( For Reference )
|
3 - yes those are the regular clock buffer cells in -buf_list |
Subject
[Stage]: Detail Router.
Describe the bug
I have implemented three designs using OpenRoad. The designs were implemented with a 65nm Technology ( Foreign PDK ).
After analysis I have found some issues :
Below I have attached screenshots of three design and the specific WNS timing paths for analysis:
Fig 1 : Design 1 ( OpenSource Design )
Fig 2 : Design 2 ( OpenSource Design )
Fig 3 : Design 3 ( OpenSource Design )
Fig 4 : Data Summary
After analysing the three designs I have the following issues and questions:
1. It is noticeable that for all three designs, openroad made some detours in the paths. Why is openroad doing this ?
2. All the designs has very high cell delay values, which is the root cause for the high slack values Why is this the case ?
Note : My observation is that there maybe a irregular correlation between placement and global routing
3. What could be some methods and solution to reduce these slack values ?
4. Can CTS be synthesized with multiple clock root buffers? Currently it takes only one
Expected Behavior
Under 500ps negetive slack.
Environment
To Reproduce
./
Relevant log output
No response
Screenshots
No response
Additional Context
No response
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