GRT Via Awareness

[osamahammad21]

Subject

[Stage]: Global Router.

Describe the bug

A change I made in drt revealed unsolvable DRC in asap7/SRAM. after isolating the issue I found that GRT's solution is the main reason behind the DRV. Here GRT is jumping from M3 to M6 in a an area filled with M4 pins. Wherever we place the via, we are always going to get a M4 spacing violation because the minspacing is 0.072 while the spacing between each 2 pins is 0.094.
The current GRT modeling is not accounting for via resources, so when it does the jump, it is not seeing the obstructions from the M4 pins
Net: _SRAM2RW16x32_O2[29]

Expected Behavior

GRT should generate acceptable guides that account for the M4 via enclosure needed for the layer jump.

Environment

[WARNING] Your current OpenROAD version is outdated.
It is recommened to pull the latest changes.
If problem persists, file a github issue with the re-producible test case.
kernel: Linux 6.2.0-33-generic
os: Ubuntu 22.04.2 LTS (Jammy Jellyfish)
cmake version 3.24.2
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To Reproduce

https://drive.google.com/file/d/1uAA-hctYAGRJ0nubhyXQZEdneQzwyYIQ/view?usp=sharing

Relevant log output

No response

Screenshots

No response

Additional Context

No response

[maliberty]

Because the pins are slightly more than min-space apart I wonder if we are miscalculating the available capacity?

[eder-matheus]

Because the pins are slightly more than min-space apart I wonder if we are miscalculating the available capacity?

The main problem is that GRT is never looking at the calculated capacity in M4 for this region because it is only going through it with the vias. Segments would not be created in these regions, but vias are. I need to update the resources modeling to account for vias obstructions.

[maliberty]

At a minimum we shouldn't put a via through a 100% blocked area. Accurate via modeling is going to be a bigger task.