Changing circuit topology during simulation

[svenboulanger]

The circuit topology can't be changed once a simulation has been started. We could include the feature of adding and removing components during the simulation (mainly transient simulations).

I foresee the following difficulties:

• Adding/removing a component mid-simulation can cause convergence problems and a severe timestep truncation in transient analysis.
• Adding/removing a component in a time analysis would need to be timestamped. If the timestep is truncated to a moment before the component is added. The component should be temporarily removed then. Can be avoided when not using timestep truncation.
• Columns and rows need to be added/removed during simulation. This is not part of the current framework. This should be done carefully to avoid creating singular matrices.
• Integration states need to be added/removed during simulation. This is not part of the current framework.
• An added element would need some kind of initial condition.

[svenboulanger]

I've been thinking about this issue lately and it seems to me that the only case where this feature is useful is for transient/time-based analysis. For DC, AC and Noise analysis, I can't find a use-case where it would make sense to change the circuit topology mid-simulation. If the circuit topology would change for those types of simulation, then it would make more sense that it influences all data points simultaneously. Only for time-based analysis you can talk about "inserting/removing an entity" mid-simulation and seeing what happens.

I've also thought about some of the foreseen difficulties:

• Convergence problems can be reduced in two ways:
  • You introduce a breakpoint at the time an entity is inserted. The simulator basically expects a bit of discontinuity afterwards.
  • You introduce a gradual influence. The entity is introduced more slowly in time avoiding a "hard" discontinuity.
• Truncation to a point before the entity is inserted can be avoided by using breakpoints too.