{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":736069632,"defaultBranch":"master","name":"dav1d-mirror","ownerLogin":"ScuffleTV","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2023-12-26T22:46:34.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/122814584?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1707940245.0","currentOid":""},"activityList":{"items":[{"before":"162fb6d85ce9e49af64ad55f1a16df1ac07067d1","after":"872e470ebf3e65b0b956f3a70329e885a2df1c2a","ref":"refs/heads/master","pushedAt":"2024-03-09T11:12:51.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"NEWS: Forgotten intro sentence","shortMessageHtmlLink":"NEWS: Forgotten intro sentence"}},{"before":"b9312c8dd890afbab5a66484bded0a1c5317fbcc","after":"162fb6d85ce9e49af64ad55f1a16df1ac07067d1","ref":"refs/heads/master","pushedAt":"2024-03-08T23:14:55.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"Update to 1.4.1","shortMessageHtmlLink":"Update to 1.4.1"}},{"before":"024b260cb94a5f6a9d7362f7b9a1539ffccb49fc","after":"b9312c8dd890afbab5a66484bded0a1c5317fbcc","ref":"refs/heads/master","pushedAt":"2024-03-08T22:50:54.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"Update THANKS.md","shortMessageHtmlLink":"Update THANKS.md"}},{"before":"0fff614a4cc6d949fa66a324c342517c86e8029e","after":"024b260cb94a5f6a9d7362f7b9a1539ffccb49fc","ref":"refs/heads/master","pushedAt":"2024-03-08T22:13:59.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm32: Fix right shifts in the 16bpc iwht implementation\n\nThese shifts used the wrong element size; this only was noticed in\nsome argon tests.","shortMessageHtmlLink":"arm32: Fix right shifts in the 16bpc iwht implementation"}},{"before":"b5b394cd6e1b49731573b55d57447fc27762ab85","after":"0fff614a4cc6d949fa66a324c342517c86e8029e","ref":"refs/heads/master","pushedAt":"2024-03-08T21:50:32.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm32/msac: Trim C functions, saves 1024 bytes","shortMessageHtmlLink":"arm32/msac: Trim C functions, saves 1024 bytes"}},{"before":"61d16e07ac05ef5686a133b44b04aba7847f04bb","after":"b5b394cd6e1b49731573b55d57447fc27762ab85","ref":"refs/heads/master","pushedAt":"2024-03-08T17:35:36.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm: Use -fno-align-functions when building\n\narm32: 2 byte alignment saves 136 bytes\narm64: 4 byte alignment saves 1200 bytes","shortMessageHtmlLink":"arm: Use -fno-align-functions when building"}},{"before":"006ca01d387ac6652825d6cce1a57b2de67dbf8d","after":"61d16e07ac05ef5686a133b44b04aba7847f04bb","ref":"refs/heads/master","pushedAt":"2024-03-08T13:36:28.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm32/itx: Trim dav1d_inv_wht4_1d_c, saves 68 bytes","shortMessageHtmlLink":"arm32/itx: Trim dav1d_inv_wht4_1d_c, saves 68 bytes"}},{"before":"932b323c3e5bbedf2c535618dbc5ad04fea2aa6e","after":"006ca01d387ac6652825d6cce1a57b2de67dbf8d","ref":"refs/heads/master","pushedAt":"2024-03-07T12:24:33.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"x86: Fix out-of-bounds read in 8bpc SSE2/SSSE3 wiener_filter\n\nWhen decoding a stream with a width of less than 4 pixels this could\ncause a segfault if the frame buffer was allocated on a page boundary.","shortMessageHtmlLink":"x86: Fix out-of-bounds read in 8bpc SSE2/SSSE3 wiener_filter"}},{"before":"b0a329d6a62410036a6947770fc0a9814d722d26","after":"932b323c3e5bbedf2c535618dbc5ad04fea2aa6e","ref":"refs/heads/master","pushedAt":"2024-03-05T12:24:11.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"AArch64: Specialise HBD Neon convolutions for 6-tap filters\n\nThe 8-tap sub-pel filters used for motion vector interpolation are:\nregular, smooth, sharp. The regular and smooth filter kernels are\nzero-padded, so they are effectively 6-tap filters (some of them are\n5-tap or even 4-tap).\n\nThis patch specialises the high bit-depth versions of put_8tap_neon\nand prep_8tap_neon functions for 6-tap filters, avoiding a lot of\nredundant work to multiply by and add zero. Wherever the sharp\nfiltering is used the 8-tap path will be always selected.\n\nBenchmarks can show a 0.5-10.8% FPS uplift highly depending on the\ninput video source. Binary size increase is ~8.5 KiB.","shortMessageHtmlLink":"AArch64: Specialise HBD Neon convolutions for 6-tap filters"}},{"before":"fd60097eb2a8be4eaf87383624c8949262d5636d","after":"b0a329d6a62410036a6947770fc0a9814d722d26","ref":"refs/heads/master","pushedAt":"2024-03-05T11:50:44.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"AArch64: Optimize 6-tap SBD HV Neon convolution\n\nOptimize the 6-tap standard bit-depth horizontal-vertical combined\nconvolution to avoid unnecessary reads and horizontal convolution\nsteps at the beginning and end of the algorithm. This also saves some\ninstructions in the final binary.\n\nPerformance of this function increases by up to 5.5% depending on\nblock size.","shortMessageHtmlLink":"AArch64: Optimize 6-tap SBD HV Neon convolution"}},{"before":"e1f80dec0006d101e5d27fbcd1b6c26cc5436227","after":"fd60097eb2a8be4eaf87383624c8949262d5636d","ref":"refs/heads/master","pushedAt":"2024-03-04T21:22:56.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"checkasm: aarch64: Print the SVE vector length, if available","shortMessageHtmlLink":"checkasm: aarch64: Print the SVE vector length, if available"}},{"before":"85a10359cdfe904af58499716cfb5dbcbf5f14c7","after":"e1f80dec0006d101e5d27fbcd1b6c26cc5436227","ref":"refs/heads/master","pushedAt":"2024-03-04T21:12:30.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"aarch64: Check for assembler support for various aarch64 extensions\n\nFirst check if the assembler supports the \".arch\" directive, and\nwhat architecture levels are supported.\n\nIn principle, we'd only need to check for support for \".arch armv8.2-a\",\nsince that's enough for enabling the i8mm and sve2 extensions.\n\nHowever, recent Clang versions (before version 17) wasn't able to\nenable the dotprod and i8mm extensions via the \".arch_extension\"\ndirectives, so check for support for armv8.4-a and armv8.6-a as well,\nwhich enable dotprod and i8mm implicitly.\n\nThis allows assembling these instructions on most commonly available\nGCC and Clang based toolchains, while still allowing toggling support\nfor the instruction sets on and off within the source files.\n\nWithin assembly, we disable these extensions by default, so that\ninstructions enabled within these extension sets can't be used\nby accident in unintended functions. Code meaning to use these\nextensions can be assembled like this:\n\n    #if HAVE_SVE\n    ENABLE_SVE\n    // code\n    DISABLE_SVE\n    #endif","shortMessageHtmlLink":"aarch64: Check for assembler support for various aarch64 extensions"}},{"before":"0d2e83cc16a127e76232c9f5aef0c8bc1b1dbe63","after":"85a10359cdfe904af58499716cfb5dbcbf5f14c7","ref":"refs/heads/master","pushedAt":"2024-02-29T00:58:36.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"checkasm: Add --list-cpuflags option\n\nPrints a list of cpuflags available for the current architecture.\n\nFlags which are supported on the current system will be printed in\ngreen, and flags which are unsupported in red with a ~ prefix.","shortMessageHtmlLink":"checkasm: Add --list-cpuflags option"}},{"before":"acc1121d2f6c0b6fb4dc0206a95c77aa2aadd762","after":"0d2e83cc16a127e76232c9f5aef0c8bc1b1dbe63","ref":"refs/heads/master","pushedAt":"2024-02-28T17:12:19.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"ci: Add an aarch64 cross compile CI job with a recent Clang","shortMessageHtmlLink":"ci: Add an aarch64 cross compile CI job with a recent Clang"}},{"before":"b7963a7389f6fc6e62d477ec8e72c066bd0ea25e","after":"acc1121d2f6c0b6fb4dc0206a95c77aa2aadd762","ref":"refs/heads/master","pushedAt":"2024-02-28T16:50:35.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"Extend Arm and AArch64 run-time CPU feature detection\n\nAdd run-time CPU feature detection for DotProd, i8mm, SVE and SVE2.\nSVE and SVE2 are AArch64-only features.","shortMessageHtmlLink":"Extend Arm and AArch64 run-time CPU feature detection"}},{"before":"52948bbfcc6903fdac0184a1a8f18236a0b34242","after":"b7963a7389f6fc6e62d477ec8e72c066bd0ea25e","ref":"refs/heads/master","pushedAt":"2024-02-27T11:50:53.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"riscv64/itx: Add 16x16 8bpc eob test\n\nKendryte K230                                         Before          After\n\ninv_txfm_add_16x16_adst_adst_0_8bpc_rvv:          1804.9 (8.45x)  1374.3 (11.18x)\ninv_txfm_add_16x16_adst_adst_1_8bpc_rvv:          1805.2 (8.45x)  1374.3 (11.17x)\ninv_txfm_add_16x16_adst_dct_0_8bpc_rvv:           1626.6 (8.92x)  1185.8 (12.22x)\ninv_txfm_add_16x16_adst_dct_1_8bpc_rvv:           1626.5 (8.91x)  1185.9 (12.22x)\ninv_txfm_add_16x16_adst_flipadst_0_8bpc_rvv:      1824.2 (8.38x)  1372.1 (11.22x)\ninv_txfm_add_16x16_adst_flipadst_1_8bpc_rvv:      1824.2 (8.37x)  1372.2 (11.21x)\ninv_txfm_add_16x16_dct_adst_0_8bpc_rvv:           1627.3 (8.94x)  1283.5 (11.29x)\ninv_txfm_add_16x16_dct_adst_1_8bpc_rvv:           1627.2 (8.95x)  1283.2 (11.29x)\ninv_txfm_add_16x16_dct_dct_0_8bpc_rvv:            1449.3 (1.08x)  1095.2 ( 1.44x)\ninv_txfm_add_16x16_dct_dct_1_8bpc_rvv:            1449.1 (9.52x)  1095.1 (12.45x)\ninv_txfm_add_16x16_dct_flipadst_0_8bpc_rvv:       1643.0 (8.87x)  1283.5 (11.29x)\ninv_txfm_add_16x16_dct_flipadst_1_8bpc_rvv:       1643.3 (8.87x)  1283.3 (11.30x)\ninv_txfm_add_16x16_dct_identity_0_8bpc_rvv:       1155.4 (9.23x)   805.9 (13.17x)\ninv_txfm_add_16x16_dct_identity_1_8bpc_rvv:       1155.4 (9.24x)   805.9 (13.17x)\ninv_txfm_add_16x16_flipadst_adst_0_8bpc_rvv:      1812.2 (8.43x)  1370.9 (11.23x)\ninv_txfm_add_16x16_flipadst_adst_1_8bpc_rvv:      1811.7 (8.44x)  1370.8 (11.24x)\ninv_txfm_add_16x16_flipadst_dct_0_8bpc_rvv:       1637.2 (8.88x)  1190.8 (12.19x)\ninv_txfm_add_16x16_flipadst_dct_1_8bpc_rvv:       1637.6 (8.87x)  1190.9 (12.19x)\ninv_txfm_add_16x16_flipadst_flipadst_0_8bpc_rvv:  1831.1 (8.34x)  1374.7 (11.21x)\ninv_txfm_add_16x16_flipadst_flipadst_1_8bpc_rvv:  1830.8 (8.35x)  1374.5 (11.22x)\ninv_txfm_add_16x16_identity_dct_0_8bpc_rvv:       1156.2 (8.67x)   948.6 (10.49x)\ninv_txfm_add_16x16_identity_dct_1_8bpc_rvv:       1156.3 (8.68x)   948.6 (10.49x)\ninv_txfm_add_16x16_identity_identity_0_8bpc_rvv:   879.3 (7.81x)   673.5 (10.28x)\ninv_txfm_add_16x16_identity_identity_1_8bpc_rvv:   879.3 (7.81x)   673.5 (10.28x)","shortMessageHtmlLink":"riscv64/itx: Add 16x16 8bpc eob test"}},{"before":"8c209190bb2da7643f8e249cac04678bb47cac0e","after":"52948bbfcc6903fdac0184a1a8f18236a0b34242","ref":"refs/heads/master","pushedAt":"2024-02-27T09:24:00.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"riscv/checkasm: Print the RVV vector length, if available","shortMessageHtmlLink":"riscv/checkasm: Print the RVV vector length, if available"}},{"before":"9d57a654e2ac315bb0293486f99cb8560e8ea75f","after":"8c209190bb2da7643f8e249cac04678bb47cac0e","ref":"refs/heads/master","pushedAt":"2024-02-26T20:14:17.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm/msac: Enable NEON optimizations on more platforms\n\nThis commit enables msac NEON assembly optimizations when building with\n MSVC targeting ARM.\nNote, the test for __APPLE__ is redundant and added for consistency.","shortMessageHtmlLink":"arm/msac: Enable NEON optimizations on more platforms"}},{"before":"2ab2ec388e8c04d03efe255d4d9303572d995a1f","after":"9d57a654e2ac315bb0293486f99cb8560e8ea75f","ref":"refs/heads/master","pushedAt":"2024-02-23T17:50:30.000Z","pushType":"push","commitsCount":3,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"CI: Add riscv64 clang build","shortMessageHtmlLink":"CI: Add riscv64 clang build"}},{"before":"36184ce06c5430b3cf7d1501d2671633d1b3f7e1","after":"2ab2ec388e8c04d03efe255d4d9303572d995a1f","ref":"refs/heads/master","pushedAt":"2024-02-22T18:16:48.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"riscv64/itx: Fix build issues with clang","shortMessageHtmlLink":"riscv64/itx: Fix build issues with clang"}},{"before":"f1d42ae8f17f889adb0b0f814cff4e8c3eb6a3b0","after":"36184ce06c5430b3cf7d1501d2671633d1b3f7e1","ref":"refs/heads/master","pushedAt":"2024-02-22T13:15:59.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"x86inc: Fix warnings with old nasm versions","shortMessageHtmlLink":"x86inc: Fix warnings with old nasm versions"}},{"before":"9cc715747f8a7e56b8d73ad3c287db98210d90f4","after":"f1d42ae8f17f889adb0b0f814cff4e8c3eb6a3b0","ref":"refs/heads/master","pushedAt":"2024-02-22T08:50:32.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"AArch64: Enable benchmarks for 8-tap sharp filters\n\nThe 6-tap sub-pel filter specialisation uses different code paths for\nsharp (8-tap) and regular/smooth (6-tap) filtering kernels.\n\nThis patch enables benchmarking for the different code paths.","shortMessageHtmlLink":"AArch64: Enable benchmarks for 8-tap sharp filters"}},{"before":"7be30df4139e66eda6ef0c00fdf530d2f3afaba2","after":"9cc715747f8a7e56b8d73ad3c287db98210d90f4","ref":"refs/heads/master","pushedAt":"2024-02-21T18:35:44.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"ppc: Factor out the shift computation","shortMessageHtmlLink":"ppc: Factor out the shift computation"}},{"before":"d22de29cad57acc6b460b1bbd93767b268713485","after":"7be30df4139e66eda6ef0c00fdf530d2f3afaba2","ref":"refs/heads/master","pushedAt":"2024-02-21T12:24:27.000Z","pushType":"push","commitsCount":21,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm64/itx16: Reuse horz_16x4 epilog, saves 96 bytes","shortMessageHtmlLink":"arm64/itx16: Reuse horz_16x4 epilog, saves 96 bytes"}},{"before":"28908b43417ae8f9f2ecbe0cc68c569d57d05e89","after":"d22de29cad57acc6b460b1bbd93767b268713485","ref":"refs/heads/master","pushedAt":"2024-02-21T11:35:42.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"Add minor msac optimizations\n\nSkip the overhead of shifting in ones into the LSB in the common case,\nthat's only required in the EOB padding. In practice this means we\nonly have to invert bits once during the refill process instead of\ntwice in every call to msac functions.\n\nAlso make some improvements to the refill asm, mainly involving\nkeeping partially inserted bytes at the end instead of clearing them.","shortMessageHtmlLink":"Add minor msac optimizations"}},{"before":"81c0b463750cbd10ad12eb44f5d60e9786bf5cc0","after":"28908b43417ae8f9f2ecbe0cc68c569d57d05e89","ref":"refs/heads/master","pushedAt":"2024-02-21T11:21:31.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"x86: Update x86inc.asm","shortMessageHtmlLink":"x86: Update x86inc.asm"}},{"before":"c15f7ecd462765a443e3d87e458de0a445c34ae7","after":"81c0b463750cbd10ad12eb44f5d60e9786bf5cc0","ref":"refs/heads/master","pushedAt":"2024-02-21T02:18:43.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"meson: Test for RISC-V assembler support\n\nSupport for '.option arch' directive [0] was added to binutils in\nd3ffd7f77654adafe5f1989bdfdbe4a337ff2e8b [1] and in llvm in\n9e8ed3403c191ab9c4903e8eeb8f732ff8a43cb4 [2].\n\n[0] https://github.com/riscv-non-isa/riscv-asm-manual/pull/67\n[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=d3ffd7f77654adafe5f1989bdfdbe4a337ff2e8b\n[2] https://github.com/llvm/llvm-project/commit/9e8ed3403c191ab9c4903e8eeb8f732ff8a43cb4","shortMessageHtmlLink":"meson: Test for RISC-V assembler support"}},{"before":"7080c090571aaf479ad3874834efb29199fff45f","after":"c15f7ecd462765a443e3d87e458de0a445c34ae7","ref":"refs/heads/master","pushedAt":"2024-02-19T15:13:47.000Z","pushType":"push","commitsCount":11,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"riscv64/itx: Add 16x8 8bpp RVV transforms\n\ninv_txfm_add_16x8_adst_adst_0_8bpc_c:             7638.9 ( 1.00x)\ninv_txfm_add_16x8_adst_adst_0_8bpc_rvv:            854.4 ( 8.94x)\ninv_txfm_add_16x8_adst_adst_1_8bpc_c:             7650.5 ( 1.00x)\ninv_txfm_add_16x8_adst_adst_1_8bpc_rvv:            854.4 ( 8.95x)\ninv_txfm_add_16x8_adst_adst_2_8bpc_c:             7649.4 ( 1.00x)\ninv_txfm_add_16x8_adst_adst_2_8bpc_rvv:            854.4 ( 8.95x)\ninv_txfm_add_16x8_adst_dct_0_8bpc_c:              7182.0 ( 1.00x)\ninv_txfm_add_16x8_adst_dct_0_8bpc_rvv:             758.1 ( 9.47x)\ninv_txfm_add_16x8_adst_dct_1_8bpc_c:              7175.6 ( 1.00x)\ninv_txfm_add_16x8_adst_dct_1_8bpc_rvv:             758.1 ( 9.47x)\ninv_txfm_add_16x8_adst_dct_2_8bpc_c:              7181.7 ( 1.00x)\ninv_txfm_add_16x8_adst_dct_2_8bpc_rvv:             758.0 ( 9.47x)\ninv_txfm_add_16x8_adst_flipadst_0_8bpc_c:         7671.7 ( 1.00x)\ninv_txfm_add_16x8_adst_flipadst_0_8bpc_rvv:        858.3 ( 8.94x)\ninv_txfm_add_16x8_adst_flipadst_1_8bpc_c:         7671.5 ( 1.00x)\ninv_txfm_add_16x8_adst_flipadst_1_8bpc_rvv:        858.1 ( 8.94x)\ninv_txfm_add_16x8_adst_flipadst_2_8bpc_c:         7673.8 ( 1.00x)\ninv_txfm_add_16x8_adst_flipadst_2_8bpc_rvv:        858.2 ( 8.94x)\ninv_txfm_add_16x8_adst_identity_0_8bpc_c:         5727.4 ( 1.00x)\ninv_txfm_add_16x8_adst_identity_0_8bpc_rvv:        612.6 ( 9.35x)\ninv_txfm_add_16x8_adst_identity_1_8bpc_c:         5709.0 ( 1.00x)\ninv_txfm_add_16x8_adst_identity_1_8bpc_rvv:        612.6 ( 9.32x)\ninv_txfm_add_16x8_adst_identity_2_8bpc_c:         5709.6 ( 1.00x)\ninv_txfm_add_16x8_adst_identity_2_8bpc_rvv:        612.5 ( 9.32x)\ninv_txfm_add_16x8_dct_adst_0_8bpc_c:              7272.9 ( 1.00x)\ninv_txfm_add_16x8_dct_adst_0_8bpc_rvv:             761.2 ( 9.55x)\ninv_txfm_add_16x8_dct_adst_1_8bpc_c:              7276.0 ( 1.00x)\ninv_txfm_add_16x8_dct_adst_1_8bpc_rvv:             761.0 ( 9.56x)\ninv_txfm_add_16x8_dct_adst_2_8bpc_c:              7271.5 ( 1.00x)\ninv_txfm_add_16x8_dct_adst_2_8bpc_rvv:             761.0 ( 9.55x)\ninv_txfm_add_16x8_dct_dct_0_8bpc_c:                822.4 ( 1.00x)\ninv_txfm_add_16x8_dct_dct_0_8bpc_rvv:              666.4 ( 1.23x)\ninv_txfm_add_16x8_dct_dct_1_8bpc_c:               6791.3 ( 1.00x)\ninv_txfm_add_16x8_dct_dct_1_8bpc_rvv:              666.6 (10.19x)\ninv_txfm_add_16x8_dct_dct_2_8bpc_c:               6786.0 ( 1.00x)\ninv_txfm_add_16x8_dct_dct_2_8bpc_rvv:              666.5 (10.18x)\ninv_txfm_add_16x8_dct_flipadst_0_8bpc_c:          7280.7 ( 1.00x)\ninv_txfm_add_16x8_dct_flipadst_0_8bpc_rvv:         764.8 ( 9.52x)\ninv_txfm_add_16x8_dct_flipadst_1_8bpc_c:          7279.0 ( 1.00x)\ninv_txfm_add_16x8_dct_flipadst_1_8bpc_rvv:         765.0 ( 9.52x)\ninv_txfm_add_16x8_dct_flipadst_2_8bpc_c:          7282.0 ( 1.00x)\ninv_txfm_add_16x8_dct_flipadst_2_8bpc_rvv:         764.8 ( 9.52x)\ninv_txfm_add_16x8_dct_identity_0_8bpc_c:          5340.5 ( 1.00x)\ninv_txfm_add_16x8_dct_identity_0_8bpc_rvv:         520.4 (10.26x)\ninv_txfm_add_16x8_dct_identity_1_8bpc_c:          5342.2 ( 1.00x)\ninv_txfm_add_16x8_dct_identity_1_8bpc_rvv:         521.0 (10.25x)\ninv_txfm_add_16x8_dct_identity_2_8bpc_c:          5341.7 ( 1.00x)\ninv_txfm_add_16x8_dct_identity_2_8bpc_rvv:         520.9 (10.25x)\ninv_txfm_add_16x8_flipadst_adst_0_8bpc_c:         7671.5 ( 1.00x)\ninv_txfm_add_16x8_flipadst_adst_0_8bpc_rvv:        855.3 ( 8.97x)\ninv_txfm_add_16x8_flipadst_adst_1_8bpc_c:         7663.0 ( 1.00x)\ninv_txfm_add_16x8_flipadst_adst_1_8bpc_rvv:        855.3 ( 8.96x)\ninv_txfm_add_16x8_flipadst_adst_2_8bpc_c:         7663.4 ( 1.00x)\ninv_txfm_add_16x8_flipadst_adst_2_8bpc_rvv:        855.2 ( 8.96x)\ninv_txfm_add_16x8_flipadst_dct_0_8bpc_c:          7185.0 ( 1.00x)\ninv_txfm_add_16x8_flipadst_dct_0_8bpc_rvv:         760.2 ( 9.45x)\ninv_txfm_add_16x8_flipadst_dct_1_8bpc_c:          7185.4 ( 1.00x)\ninv_txfm_add_16x8_flipadst_dct_1_8bpc_rvv:         760.2 ( 9.45x)\ninv_txfm_add_16x8_flipadst_dct_2_8bpc_c:          7185.3 ( 1.00x)\ninv_txfm_add_16x8_flipadst_dct_2_8bpc_rvv:         760.4 ( 9.45x)\ninv_txfm_add_16x8_flipadst_flipadst_0_8bpc_c:     7686.6 ( 1.00x)\ninv_txfm_add_16x8_flipadst_flipadst_0_8bpc_rvv:    859.1 ( 8.95x)\ninv_txfm_add_16x8_flipadst_flipadst_1_8bpc_c:     7687.9 ( 1.00x)\ninv_txfm_add_16x8_flipadst_flipadst_1_8bpc_rvv:    859.2 ( 8.95x)\ninv_txfm_add_16x8_flipadst_flipadst_2_8bpc_c:     7684.5 ( 1.00x)\ninv_txfm_add_16x8_flipadst_flipadst_2_8bpc_rvv:    859.0 ( 8.95x)\ninv_txfm_add_16x8_flipadst_identity_0_8bpc_c:     5723.1 ( 1.00x)\ninv_txfm_add_16x8_flipadst_identity_0_8bpc_rvv:    615.7 ( 9.30x)\ninv_txfm_add_16x8_flipadst_identity_1_8bpc_c:     5725.1 ( 1.00x)\ninv_txfm_add_16x8_flipadst_identity_1_8bpc_rvv:    615.6 ( 9.30x)\ninv_txfm_add_16x8_flipadst_identity_2_8bpc_c:     5713.0 ( 1.00x)\ninv_txfm_add_16x8_flipadst_identity_2_8bpc_rvv:    615.6 ( 9.28x)\ninv_txfm_add_16x8_identity_adst_0_8bpc_c:         5390.1 ( 1.00x)\ninv_txfm_add_16x8_identity_adst_0_8bpc_rvv:        617.9 ( 8.72x)\ninv_txfm_add_16x8_identity_adst_1_8bpc_c:         5388.8 ( 1.00x)\ninv_txfm_add_16x8_identity_adst_1_8bpc_rvv:        617.7 ( 8.72x)\ninv_txfm_add_16x8_identity_adst_2_8bpc_c:         5390.0 ( 1.00x)\ninv_txfm_add_16x8_identity_adst_2_8bpc_rvv:        617.7 ( 8.73x)\ninv_txfm_add_16x8_identity_dct_0_8bpc_c:          4919.0 ( 1.00x)\ninv_txfm_add_16x8_identity_dct_0_8bpc_rvv:         522.9 ( 9.41x)\ninv_txfm_add_16x8_identity_dct_1_8bpc_c:          4916.6 ( 1.00x)\ninv_txfm_add_16x8_identity_dct_1_8bpc_rvv:         523.0 ( 9.40x)\ninv_txfm_add_16x8_identity_dct_2_8bpc_c:          4918.6 ( 1.00x)\ninv_txfm_add_16x8_identity_dct_2_8bpc_rvv:         523.0 ( 9.40x)\ninv_txfm_add_16x8_identity_flipadst_0_8bpc_c:     5402.3 ( 1.00x)\ninv_txfm_add_16x8_identity_flipadst_0_8bpc_rvv:    621.7 ( 8.69x)\ninv_txfm_add_16x8_identity_flipadst_1_8bpc_c:     5402.1 ( 1.00x)\ninv_txfm_add_16x8_identity_flipadst_1_8bpc_rvv:    621.3 ( 8.69x)\ninv_txfm_add_16x8_identity_flipadst_2_8bpc_c:     5401.6 ( 1.00x)\ninv_txfm_add_16x8_identity_flipadst_2_8bpc_rvv:    621.6 ( 8.69x)\ninv_txfm_add_16x8_identity_identity_0_8bpc_c:     3436.1 ( 1.00x)\ninv_txfm_add_16x8_identity_identity_0_8bpc_rvv:    377.8 ( 9.09x)\ninv_txfm_add_16x8_identity_identity_1_8bpc_c:     3436.3 ( 1.00x)\ninv_txfm_add_16x8_identity_identity_1_8bpc_rvv:    377.9 ( 9.09x)\ninv_txfm_add_16x8_identity_identity_2_8bpc_c:     3436.1 ( 1.00x)\ninv_txfm_add_16x8_identity_identity_2_8bpc_rvv:    377.8 ( 9.09x)","shortMessageHtmlLink":"riscv64/itx: Add 16x8 8bpp RVV transforms"}},{"before":"50d63f9a6efdc981ed204a2b5088d133d341141a","after":"7080c090571aaf479ad3874834efb29199fff45f","ref":"refs/heads/master","pushedAt":"2024-02-19T14:13:13.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"riscv64/itx: Reuse 8x8 epilog, saves 306 bytes\n\nThis commit shares the trailing instructions from inv_txfm_add_8x8_rvv\n with inv_txfm_identity_add_8x8_rvv, only *8x8_identity* functions are\n modified:\n\n                                                   Old     New    Delta\n\ninv_txfm_add_8x8_identity_adst_0_8bpc_rvv:        268.2   268.2   0.00%\ninv_txfm_add_8x8_identity_adst_1_8bpc_rvv:        268.3   268.2  -0.04%\ninv_txfm_add_8x8_identity_dct_0_8bpc_rvv:         225.1   228.3   1.42%\ninv_txfm_add_8x8_identity_dct_1_8bpc_rvv:         225.1   228.2   1.37%\ninv_txfm_add_8x8_identity_flipadst_0_8bpc_rvv:    270.6   270.2  -0.15%\ninv_txfm_add_8x8_identity_flipadst_1_8bpc_rvv:    270.6   270.3  -0.11%\ninv_txfm_add_8x8_identity_identity_0_8bpc_rvv:    146.1   146.0  -0.07%\ninv_txfm_add_8x8_identity_identity_1_8bpc_rvv:    146.1   146.1   0.00%\n\ninv_txfm_add_8x8_dct_adst_0_8bpc_rvv:             360.0   359.8  -0.06%\ninv_txfm_add_8x8_dct_adst_1_8bpc_rvv:             360.0   359.6  -0.11%\ninv_txfm_add_8x8_dct_dct_0_8bpc_rvv:               74.7    76.4   2.28%\ninv_txfm_add_8x8_dct_dct_1_8bpc_rvv:              316.9   321.6   1.48%\ninv_txfm_add_8x8_dct_flipadst_0_8bpc_rvv:         362.0   361.8  -0.06%\ninv_txfm_add_8x8_dct_flipadst_1_8bpc_rvv:         361.9   361.9   0.00%\ninv_txfm_add_8x8_dct_identity_0_8bpc_rvv:         240.0   240.6   0.25%\ninv_txfm_add_8x8_dct_identity_1_8bpc_rvv:         240.0   240.6   0.25%\n\ninv_txfm_add_8x8_adst_adst_0_8bpc_rvv:            403.0   403.3   0.07%\ninv_txfm_add_8x8_adst_adst_1_8bpc_rvv:            403.0   403.4   0.10%\ninv_txfm_add_8x8_adst_dct_0_8bpc_rvv:             359.7   359.7   0.00%\ninv_txfm_add_8x8_adst_dct_1_8bpc_rvv:             359.4   359.7   0.08%\ninv_txfm_add_8x8_adst_flipadst_0_8bpc_rvv:        404.6   405.1   0.12%\ninv_txfm_add_8x8_adst_flipadst_1_8bpc_rvv:        404.6   405.3   0.17%\ninv_txfm_add_8x8_adst_identity_0_8bpc_rvv:        283.4   282.8  -0.21%\ninv_txfm_add_8x8_adst_identity_1_8bpc_rvv:        283.4   282.8  -0.21%\n\ninv_txfm_add_8x8_flipadst_adst_0_8bpc_rvv:        403.9   404.6   0.17%\ninv_txfm_add_8x8_flipadst_adst_1_8bpc_rvv:        404.0   404.6   0.15%\ninv_txfm_add_8x8_flipadst_dct_0_8bpc_rvv:         361.4   361.5   0.03%\ninv_txfm_add_8x8_flipadst_dct_1_8bpc_rvv:         361.3   361.5   0.06%\ninv_txfm_add_8x8_flipadst_flipadst_0_8bpc_rvv:    406.2   406.1  -0.02%\ninv_txfm_add_8x8_flipadst_flipadst_1_8bpc_rvv:    405.7   406.4   0.17%\ninv_txfm_add_8x8_flipadst_identity_0_8bpc_rvv:    284.8   287.5   0.95%\ninv_txfm_add_8x8_flipadst_identity_1_8bpc_rvv:    284.8   287.6   0.98%","shortMessageHtmlLink":"riscv64/itx: Reuse 8x8 epilog, saves 306 bytes"}},{"before":"4796b59fc0a459588183dc2ea199ba1074befc67","after":"50d63f9a6efdc981ed204a2b5088d133d341141a","ref":"refs/heads/master","pushedAt":"2024-02-19T13:14:36.000Z","pushType":"push","commitsCount":2,"pusher":{"login":"TroyKomodo","name":"Troy","path":"/TroyKomodo","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/49777269?s=80&v=4"},"commit":{"message":"arm32/itx: Only set r4 when needed, saves 48 bytes\n\nAvoid setting r4 when the horizontal transform is the identity in\n {4,8}x16 and 16x4 rectangular transforms.","shortMessageHtmlLink":"arm32/itx: Only set r4 when needed, saves 48 bytes"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEEORQMQA","startCursor":null,"endCursor":null}},"title":"Activity · ScuffleTV/dav1d-mirror"}