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Added SPI to Single Core Design and it hangs in SoftConsole #10

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salmansheikh opened this issue Nov 19, 2018 · 15 comments
Open

Added SPI to Single Core Design and it hangs in SoftConsole #10

salmansheikh opened this issue Nov 19, 2018 · 15 comments
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@CLappin

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@salmansheikh
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I only added a single CoreSPI to the Single Processor design, it compiled, placed and routed (I even assigned pins to the SPI signals). Programmed the board and when I try to start the debugger, I can't get anything to work. It hangs with a msg. Is there something that I did wrong in h/w or SoftConsole that would give this error. I've been fighting this for a week with no clue what is wrong and why it doesn't even enter debug like the normal pre-built FPGA image for a single core.

Attached is what SoftConsole says when I try to run debug to test my core. Or even if I try running even the blinky program (which should still work since its just adding an SPI core). Nothing runs on this version.

error_on_debug
@salmansheikh
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Normally, i should see a bunch of register values in the debugger when I run the pre-built FPGA image for the RTG4 . How are those normally printed? Is that a openocd command that prints those? It gives an error that I can't even get a google answer for what E0E means.

@salmansheikh
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Here is my smartdesign. Its only different from the base design by the addition of the CoreSPI to CoreAPB3 bus and some output pins for SPI.

added_spi.pdf

@CLappin
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CLappin commented Nov 20, 2018

Hi,

Could you try updating the RISCV hal to version 2.2.103 from Firmware Catalog, it's under RISC-V Hardware Abstraction Layer (HAL), as the project you generated was for SoftConsole v5.2.

If this does not work, could you send me a link to your Libero project and I'll take a look at it.

Thanks,
Ciaran

@CLappin CLappin self-assigned this Nov 20, 2018
@salmansheikh
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Is this done in SoftConsole?

@salmansheikh
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How do I generate a hw_platform.h? Or what tool does that?

@CLappin
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CLappin commented Nov 20, 2018

Yes, the riscv hal is generated in Firmware Catalog which comes with Libero SoC v11.9. The riscv hal is then replaced in the example firmware project that you generated from the firmware catalog before.

The hw_platform.h can be taken from one of the example projects in SoftConsole v5.3. If I remember correctly there should be a sample hw_platform.h file in the riscv hal. Depending on your design you may need to update the hw_platform.h file to match your design. For example, the example hw_platform.h file has the UART at 0x70001000 your design may have it at 0x6000F000, you would have to change the define related to the UART so it matches your design.

@salmansheikh
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It built but still having the same issue in the debugger.

17:53:37 **** Build of configuration Debug for project miv-rv32im ****
make all
Building file: ../src/main.c
Invoking: GNU RISC-V Cross C Compiler
riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -msmall-data-limit=8 -O2 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\drivers\CoreGPIO" -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im" -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\drivers\CoreSPI" -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\drivers\CoreUARTapb" -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\hal" -I"C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\riscv_hal" -std=gnu11 -MMD -MP -MF"src/main.d" -MT"src/main.o" -c -o "src/main.o" "../src/main.c"
Finished building: ../src/main.c

Building target: miv-rv32im.elf
Invoking: GNU RISC-V Cross C Linker
riscv64-unknown-elf-gcc -march=rv32im -mabi=ilp32 -msmall-data-limit=8 -O2 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -T "C:\Users\ssheikh\Documents\SoftConsole2\miv-rv32im\riscv_hal\microsemi-riscv-ram.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"miv-rv32im.map" --specs=nano.specs -o "miv-rv32im.elf" ./src/main.o
c:/microsemi/softconsole_v5.3/riscv-unknown-elf-gcc/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld.exe: warning: cannot find entry symbol _start; defaulting to 0000000080000000
Finished building target: miv-rv32im.elf

I can't attach the zip file. Its 117MB for the Libero project.

@salmansheikh
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The link to the project file is here.

https://www.dropbox.com/s/a4ykfqzuc1g3ik5/MIV_RV32IMA_BaseDesign_vlog.zip?dl=0

And here is the softconsole zip file:

https://www.dropbox.com/s/xzm1it82fuvbbex/spi_workspace.zip?dl=0

@salmansheikh
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okay, I found one thing my clock should be 100MHz not 50MHz for system in hw_platform.h since that is the GL0 going to the other blocks. How do I know what my address is for my components? I don't see any memory map file generated by SmartDesign or LiberoSOC. Also I keep getting a warning about the _start and the address 80000000 is the default.

c:/microsemi/softconsole_v5.3/riscv-unknown-elf-gcc/bin/../lib/gcc/riscv64-unknown-elf/7.2.0/../../../../riscv64-unknown-elf/bin/ld.exe: warning: cannot find entry symbol _start; defaulting to 0000000080000000

Is this supposed to be the reset address. From Libero this value is 80808080. How can I change it to that in softconsole?
reset

@CLappin
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CLappin commented Nov 21, 2018

Hi ,

I have had a look at your Libero project and have noticed the following:

  1. the design is attempting to run at 100Mhz, this is not possible with this MIV core. I reduced the frequency to 50Mhz and I was able to run the example firmware supplied with SoftConsole 5.3. Please refer to the MIV_RV32IMA_L1_AHB Usage Table for a list of operating frequencies.

  2. The MIV_RV32IMA_L1_AHB core that you are using has an issue with the reset, this can be fixed by reverting to the MIV_RV32IMA_L1_AHB v2.0.100 or by applying the following fix to the miv_rv32ima_l1_ahb_async_reset_reg.v file. Find the always@ block and change it to read always@(posedge clk or posedge rst) begin. This issue has been flagged and there will be a fix released in the coming weeks.

  3. I suggest using a reset vector of the MIV to 0x8000_0000.

I haven't had a chance to look at your firmware.

Please attempt these fixes and let me know if you can get a debug session going.

@salmansheikh
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salmansheikh commented Nov 26, 2018 via email

@salmansheikh
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salmansheikh commented Nov 26, 2018 via email

@salmansheikh
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salmansheikh commented Nov 27, 2018 via email

@CLappin
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CLappin commented Nov 28, 2018

Hi,

which message are you referring to?
There is a known issue stated in the Hand Book for the MiV cores ( section 10.1 ) that says you've to reset/power cycle the board between debug sessions sometimes.

@salmansheikh
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salmansheikh commented Nov 28, 2018 via email

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