{"payload":{"header_redesign_enabled":false,"results":[{"id":"445532960","archived":false,"color":"#adb2cb","followers":44,"has_funding_file":false,"hl_name":"MJoergen/HyperRAM","hl_trunc_description":"Portable HyperRAM controller","language":"VHDL","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":445532960,"name":"HyperRAM","owner_id":1299486,"owner_login":"MJoergen","updated_at":"2024-05-06T13:45:11.558Z","has_issues":true}},"sponsorable":false,"topics":["fpga","vhdl","intel","xilinx","vivado","altera","lattice","modelsim","questasim","avalon","quartus","artix","questa","hyperram"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AMJoergen%252FHyperRAM%2B%2Blanguage%253AVHDL","metadata":null,"csrf_tokens":{"/MJoergen/HyperRAM/star":{"post":"k1dxmnrGYtU59NCPeOAs78R9SQ6JNa7h1xnXb_--31x-dNjzK3_J1RYGVk5OJyNtbEiVQSS6M84Pq2zW3fm9Sg"},"/MJoergen/HyperRAM/unstar":{"post":"5Fyl4aFo9DzzgkloF-w9UpUqgdvvyJWAbbNvP-XxECkY7mWQV2KnHgbTiZyBOTvIDxVBCweA-IdJfRy2xXGcrQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"bLdMLzd8U7XwEULsII3NLZUayNEW-gJcQkpHvzqejESf6j09f2NB8iqBYf-pRG9ulWe22sY3n8x9rJ0QWs85gQ"}}},"title":"Repository search results"}