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Polaris 116080201 is too slow. #3

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sam-falvo opened this issue Oct 8, 2016 · 1 comment
Open

Polaris 116080201 is too slow. #3

sam-falvo opened this issue Oct 8, 2016 · 1 comment
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New Feature or Bug Fix

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@sam-falvo
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If synthesized on an iCE40HX-8K device, icetime reports that the chip is too slow to run a minimal Kestrel-3 operating environment at the desired instruction execution rate.

Total path delay: 40.85 ns (24.48 MHz)

This needs to be at least 30MHz for me to feel confident that we can deliver 6 MIPS.
@sam-falvo
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// Reading input .asc file..
// Reading 8k chipdb file..
// Creating timing netlist..

icetime topological timing analysis report
==========================================

Warning: This timing analysis report is an estimate!
Info: max_span_hack is enabled: estimate is conservative.

Report for critical path:
-------------------------

        lc40_6_19_6 (LogicCell40) [clk] -> lcout: 0.640 ns
     0.640 ns net_22713 (p.rst)
        odrv_6_19_22713_26812 (Odrv4) I -> O: 0.372 ns
        t4238 (Span4Mux_v4) I -> O: 0.372 ns
        t4237 (Span4Mux_v4) I -> O: 0.372 ns
        t4254 (Span4Mux_h4) I -> O: 0.316 ns
        t4260 (Span4Mux_h4) I -> O: 0.316 ns
        t4263 (Span4Mux_h4) I -> O: 0.316 ns
        t4271 (Span4Mux_v4) I -> O: 0.372 ns
        t4292 (Span4Mux_h4) I -> O: 0.316 ns
        t4291 (Span4Mux_h4) I -> O: 0.316 ns
        t4290 (Span4Mux_v4) I -> O: 0.372 ns
        t4289 (Span4Mux_v4) I -> O: 0.372 ns
        t4288 (Span4Mux_v4) I -> O: 0.372 ns
        t4287 (Span4Mux_h4) I -> O: 0.316 ns
        t4286 (Span4Mux_v4) I -> O: 0.372 ns
        t4285 (Span4Mux_h4) I -> O: 0.316 ns
        t4284 (IoSpan4Mux) I -> O: 0.323 ns
        t4329 (Span4Mux_v4) I -> O: 0.372 ns
        t4328 (LocalMux) I -> O: 0.330 ns
        inmux_29_20_119385_119422 (InMux) I -> O: 0.260 ns
        lc40_29_20_3 (LogicCell40) in0 -> lcout: 0.449 ns
     7.555 ns net_115256 ($abc$12771$n1739)
        odrv_29_20_115256_115038 (Odrv4) I -> O: 0.372 ns
        t21232 (LocalMux) I -> O: 0.330 ns
        inmux_28_18_115062_115099 (InMux) I -> O: 0.260 ns
        lc40_28_18_3 (LogicCell40) in0 -> lcout: 0.449 ns
     8.965 ns net_110933 ($abc$12771$n1780_1)
        odrv_28_18_110933_110715 (Odrv4) I -> O: 0.372 ns
        t20204 (LocalMux) I -> O: 0.330 ns
        inmux_28_16_114824_114844 (InMux) I -> O: 0.260 ns
        lc40_28_16_1 (LogicCell40) in3 -> lcout: 0.316 ns
    10.241 ns net_110685 ($abc$12771$n1779)
        odrv_28_16_110685_95181 (Odrv12) I -> O: 0.540 ns
        t19795 (LocalMux) I -> O: 0.330 ns
        inmux_23_16_95099_95135 (InMux) I -> O: 0.260 ns
        lc40_23_16_2 (LogicCell40) in0 -> lcout: 0.449 ns
    11.819 ns net_90974 ($abc$12771$n1778_1)
        odrv_23_16_90974_95190 (Odrv4) I -> O: 0.372 ns
        t14154 (Span4Mux_v4) I -> O: 0.372 ns
        t14153 (LocalMux) I -> O: 0.330 ns
        inmux_27_17_110865_110906 (InMux) I -> O: 0.260 ns
        lc40_27_17_4 (LogicCell40) in1 -> lcout: 0.400 ns
    13.552 ns net_106734 ($abc$12771$n1777)
        odrv_27_17_106734_109957 (Odrv12) I -> O: 0.540 ns
        t18682 (Span12Mux_h12) I -> O: 0.540 ns
        t18685 (Span12Mux_v12) I -> O: 0.540 ns
        t18729 (Sp12to4) I -> O: 0.449 ns
        t18728 (Span4Mux_h4) I -> O: 0.316 ns
        t18727 (Span4Mux_v4) I -> O: 0.372 ns
        t18726 (Span4Mux_v4) I -> O: 0.372 ns
        t18725 (Span4Mux_h4) I -> O: 0.316 ns
        t18730 (LocalMux) I -> O: 0.330 ns
        inmux_16_5_65211_65274 (InMux) I -> O: 0.260 ns
        lc40_16_5_7 (LogicCell40) in0 -> lcout: 0.449 ns
    18.033 ns net_61089 (p.alu.b[1])
        odrv_16_5_61089_61239 (Odrv4) I -> O: 0.372 ns
        t8573 (LocalMux) I -> O: 0.330 ns
        inmux_16_8_65571_65614 (InMux) I -> O: 0.260 ns
        lc40_16_8_2 (LogicCell40) in1 -> carryout: 0.260 ns
    19.254 ns net_65612 ($auto$alumacc.cc:470:replace_alu$1417.C[2])
        lc40_16_8_3 (LogicCell40) carryin -> carryout: 0.126 ns
    19.380 ns net_65618 ($auto$alumacc.cc:470:replace_alu$1417.C[3])
        lc40_16_8_4 (LogicCell40) carryin -> carryout: 0.126 ns
    19.506 ns net_65624 ($auto$alumacc.cc:470:replace_alu$1417.C[4])
        lc40_16_8_5 (LogicCell40) carryin -> carryout: 0.126 ns
    19.632 ns net_65630 ($auto$alumacc.cc:470:replace_alu$1417.C[5])
        lc40_16_8_6 (LogicCell40) carryin -> carryout: 0.126 ns
    19.759 ns net_65636 ($auto$alumacc.cc:470:replace_alu$1417.C[6])
        lc40_16_8_7 (LogicCell40) carryin -> carryout: 0.126 ns
    19.885 ns net_65642 ($auto$alumacc.cc:470:replace_alu$1417.C[7])
        t1133 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_9_0 (LogicCell40) carryin -> carryout: 0.126 ns
    20.208 ns net_65723 ($auto$alumacc.cc:470:replace_alu$1417.C[8])
        lc40_16_9_1 (LogicCell40) carryin -> carryout: 0.126 ns
    20.334 ns net_65729 ($auto$alumacc.cc:470:replace_alu$1417.C[9])
        lc40_16_9_2 (LogicCell40) carryin -> carryout: 0.126 ns
    20.460 ns net_65735 ($auto$alumacc.cc:470:replace_alu$1417.C[10])
        lc40_16_9_3 (LogicCell40) carryin -> carryout: 0.126 ns
    20.586 ns net_65741 ($auto$alumacc.cc:470:replace_alu$1417.C[11])
        lc40_16_9_4 (LogicCell40) carryin -> carryout: 0.126 ns
    20.713 ns net_65747 ($auto$alumacc.cc:470:replace_alu$1417.C[12])
        lc40_16_9_5 (LogicCell40) carryin -> carryout: 0.126 ns
    20.839 ns net_65753 ($auto$alumacc.cc:470:replace_alu$1417.C[13])
        lc40_16_9_6 (LogicCell40) carryin -> carryout: 0.126 ns
    20.965 ns net_65759 ($auto$alumacc.cc:470:replace_alu$1417.C[14])
        lc40_16_9_7 (LogicCell40) carryin -> carryout: 0.126 ns
    21.091 ns net_65765 ($auto$alumacc.cc:470:replace_alu$1417.C[15])
        t1142 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_10_0 (LogicCell40) carryin -> carryout: 0.126 ns
    21.414 ns net_65846 ($auto$alumacc.cc:470:replace_alu$1417.C[16])
        lc40_16_10_1 (LogicCell40) carryin -> carryout: 0.126 ns
    21.540 ns net_65852 ($auto$alumacc.cc:470:replace_alu$1417.C[17])
        lc40_16_10_2 (LogicCell40) carryin -> carryout: 0.126 ns
    21.666 ns net_65858 ($auto$alumacc.cc:470:replace_alu$1417.C[18])
        lc40_16_10_3 (LogicCell40) carryin -> carryout: 0.126 ns
    21.793 ns net_65864 ($auto$alumacc.cc:470:replace_alu$1417.C[19])
        lc40_16_10_4 (LogicCell40) carryin -> carryout: 0.126 ns
    21.919 ns net_65870 ($auto$alumacc.cc:470:replace_alu$1417.C[20])
        lc40_16_10_5 (LogicCell40) carryin -> carryout: 0.126 ns
    22.045 ns net_65876 ($auto$alumacc.cc:470:replace_alu$1417.C[21])
        lc40_16_10_6 (LogicCell40) carryin -> carryout: 0.126 ns
    22.171 ns net_65882 ($auto$alumacc.cc:470:replace_alu$1417.C[22])
        lc40_16_10_7 (LogicCell40) carryin -> carryout: 0.126 ns
    22.298 ns net_65888 ($auto$alumacc.cc:470:replace_alu$1417.C[23])
        t1148 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_11_0 (LogicCell40) carryin -> carryout: 0.126 ns
    22.620 ns net_65969 ($auto$alumacc.cc:470:replace_alu$1417.C[24])
        lc40_16_11_1 (LogicCell40) carryin -> carryout: 0.126 ns
    22.746 ns net_65975 ($auto$alumacc.cc:470:replace_alu$1417.C[25])
        lc40_16_11_2 (LogicCell40) carryin -> carryout: 0.126 ns
    22.873 ns net_65981 ($auto$alumacc.cc:470:replace_alu$1417.C[26])
        lc40_16_11_3 (LogicCell40) carryin -> carryout: 0.126 ns
    22.999 ns net_65987 ($auto$alumacc.cc:470:replace_alu$1417.C[27])
        lc40_16_11_4 (LogicCell40) carryin -> carryout: 0.126 ns
    23.125 ns net_65993 ($auto$alumacc.cc:470:replace_alu$1417.C[28])
        lc40_16_11_5 (LogicCell40) carryin -> carryout: 0.126 ns
    23.251 ns net_65999 ($auto$alumacc.cc:470:replace_alu$1417.C[29])
        lc40_16_11_6 (LogicCell40) carryin -> carryout: 0.126 ns
    23.378 ns net_66005 ($auto$alumacc.cc:470:replace_alu$1417.C[30])
        lc40_16_11_7 (LogicCell40) carryin -> carryout: 0.126 ns
    23.504 ns net_66011 ($auto$alumacc.cc:470:replace_alu$1417.C[31])
        t1156 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_12_0 (LogicCell40) carryin -> carryout: 0.126 ns
    23.826 ns net_66092 ($auto$alumacc.cc:470:replace_alu$1417.C[32])
        lc40_16_12_1 (LogicCell40) carryin -> carryout: 0.126 ns
    23.953 ns net_66098 ($auto$alumacc.cc:470:replace_alu$1417.C[33])
        lc40_16_12_2 (LogicCell40) carryin -> carryout: 0.126 ns
    24.079 ns net_66104 ($auto$alumacc.cc:470:replace_alu$1417.C[34])
        lc40_16_12_3 (LogicCell40) carryin -> carryout: 0.126 ns
    24.205 ns net_66110 ($auto$alumacc.cc:470:replace_alu$1417.C[35])
        lc40_16_12_4 (LogicCell40) carryin -> carryout: 0.126 ns
    24.331 ns net_66116 ($auto$alumacc.cc:470:replace_alu$1417.C[36])
        lc40_16_12_5 (LogicCell40) carryin -> carryout: 0.126 ns
    24.458 ns net_66122 ($auto$alumacc.cc:470:replace_alu$1417.C[37])
        lc40_16_12_6 (LogicCell40) carryin -> carryout: 0.126 ns
    24.584 ns net_66128 ($auto$alumacc.cc:470:replace_alu$1417.C[38])
        lc40_16_12_7 (LogicCell40) carryin -> carryout: 0.126 ns
    24.710 ns net_66134 ($auto$alumacc.cc:470:replace_alu$1417.C[39])
        t1163 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_13_0 (LogicCell40) carryin -> carryout: 0.126 ns
    25.033 ns net_66215 ($auto$alumacc.cc:470:replace_alu$1417.C[40])
        lc40_16_13_1 (LogicCell40) carryin -> carryout: 0.126 ns
    25.159 ns net_66221 ($auto$alumacc.cc:470:replace_alu$1417.C[41])
        lc40_16_13_2 (LogicCell40) carryin -> carryout: 0.126 ns
    25.285 ns net_66227 ($auto$alumacc.cc:470:replace_alu$1417.C[42])
        lc40_16_13_3 (LogicCell40) carryin -> carryout: 0.126 ns
    25.411 ns net_66233 ($auto$alumacc.cc:470:replace_alu$1417.C[43])
        lc40_16_13_4 (LogicCell40) carryin -> carryout: 0.126 ns
    25.538 ns net_66239 ($auto$alumacc.cc:470:replace_alu$1417.C[44])
        lc40_16_13_5 (LogicCell40) carryin -> carryout: 0.126 ns
    25.664 ns net_66245 ($auto$alumacc.cc:470:replace_alu$1417.C[45])
        lc40_16_13_6 (LogicCell40) carryin -> carryout: 0.126 ns
    25.790 ns net_66251 ($auto$alumacc.cc:470:replace_alu$1417.C[46])
        lc40_16_13_7 (LogicCell40) carryin -> carryout: 0.126 ns
    25.916 ns net_66257 ($auto$alumacc.cc:470:replace_alu$1417.C[47])
        t1171 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_14_0 (LogicCell40) carryin -> carryout: 0.126 ns
    26.239 ns net_66338 ($auto$alumacc.cc:470:replace_alu$1417.C[48])
        lc40_16_14_1 (LogicCell40) carryin -> carryout: 0.126 ns
    26.365 ns net_66344 ($auto$alumacc.cc:470:replace_alu$1417.C[49])
        lc40_16_14_2 (LogicCell40) carryin -> carryout: 0.126 ns
    26.492 ns net_66350 ($auto$alumacc.cc:470:replace_alu$1417.C[50])
        lc40_16_14_3 (LogicCell40) carryin -> carryout: 0.126 ns
    26.618 ns net_66356 ($auto$alumacc.cc:470:replace_alu$1417.C[51])
        lc40_16_14_4 (LogicCell40) carryin -> carryout: 0.126 ns
    26.744 ns net_66362 ($auto$alumacc.cc:470:replace_alu$1417.C[52])
        lc40_16_14_5 (LogicCell40) carryin -> carryout: 0.126 ns
    26.870 ns net_66368 ($auto$alumacc.cc:470:replace_alu$1417.C[53])
        lc40_16_14_6 (LogicCell40) carryin -> carryout: 0.126 ns
    26.997 ns net_66374 ($auto$alumacc.cc:470:replace_alu$1417.C[54])
        lc40_16_14_7 (LogicCell40) carryin -> carryout: 0.126 ns
    27.123 ns net_66380 ($auto$alumacc.cc:470:replace_alu$1417.C[55])
        t1178 (ICE_CARRY_IN_MUX) carryinitin -> carryinitout: 0.196 ns
        lc40_16_15_0 (LogicCell40) carryin -> carryout: 0.126 ns
    27.445 ns net_66461 ($auto$alumacc.cc:470:replace_alu$1417.C[56])
        lc40_16_15_1 (LogicCell40) carryin -> carryout: 0.126 ns
    27.572 ns net_66467 ($auto$alumacc.cc:470:replace_alu$1417.C[57])
        lc40_16_15_2 (LogicCell40) carryin -> carryout: 0.126 ns
    27.698 ns net_66473 ($auto$alumacc.cc:470:replace_alu$1417.C[58])
        inmux_16_15_66473_66483 (InMux) I -> O: 0.260 ns
        lc40_16_15_3 (LogicCell40) in3 -> lcout: 0.316 ns
    28.273 ns net_62315 (p.alu.sumL[58])
        odrv_16_15_62315_62450 (Odrv4) I -> O: 0.372 ns
        t8686 (LocalMux) I -> O: 0.330 ns
        inmux_18_15_74612_74654 (InMux) I -> O: 0.260 ns
        lc40_18_15_6 (LogicCell40) in3 -> lcout: 0.316 ns
    29.549 ns net_70471 ($abc$12771$n2684)
        t9668 (LocalMux) I -> O: 0.330 ns
        inmux_18_15_74596_74630 (InMux) I -> O: 0.260 ns
        lc40_18_15_2 (LogicCell40) in3 -> lcout: 0.316 ns
    30.454 ns net_70467 ($abc$12771$n2683)
        t9665 (LocalMux) I -> O: 0.330 ns
        inmux_19_15_78669_78707 (InMux) I -> O: 0.260 ns
        lc40_19_15_2 (LogicCell40) in3 -> lcout: 0.316 ns
    31.359 ns net_74543 ($abc$12771$n2682)
        odrv_19_15_74543_77522 (Odrv12) I -> O: 0.540 ns
        t10239 (Span12Mux_h12) I -> O: 0.540 ns
        t10238 (Sp12to4) I -> O: 0.449 ns
        t10237 (Span4Mux_v4) I -> O: 0.372 ns
        t10236 (Span4Mux_v4) I -> O: 0.372 ns
        t10235 (LocalMux) I -> O: 0.330 ns
        inmux_26_23_107525_107542 (InMux) I -> O: 0.260 ns
        lc40_26_23_0 (LogicCell40) in0 -> lcout: 0.449 ns
    34.669 ns net_103571 ($abc$12771$n3143)
        odrv_26_23_103571_100132 (Odrv4) I -> O: 0.372 ns
        t18270 (Span4Mux_v4) I -> O: 0.372 ns
        t18269 (LocalMux) I -> O: 0.330 ns
        inmux_24_27_100520_100560 (InMux) I -> O: 0.260 ns
        lc40_24_27_1 (LogicCell40) in1 -> lcout: 0.400 ns
    36.402 ns net_96403 ($abc$12771$n4843)
        odrv_24_27_96403_80226 (Odrv12) I -> O: 0.540 ns
        t16615 (Sp12to4) I -> O: 0.449 ns
        t16614 (Span4Mux_v4) I -> O: 0.372 ns
        t16613 (Span4Mux_v4) I -> O: 0.372 ns
        t16612 (Span4Mux_h4) I -> O: 0.316 ns
        t16611 (Span4Mux_v4) I -> O: 0.372 ns
        t16610 (LocalMux) I -> O: 0.330 ns
        inmux_26_28_108148_108175 (InMux) I -> O: 0.260 ns
        lc40_26_28_3 (LogicCell40) in0 -> lcout: 0.449 ns
    39.859 ns net_104084 (p.csrs.cdat_i[58])
        t18367 (LocalMux) I -> O: 0.330 ns
        inmux_27_27_112105_112123 (InMux) I -> O: 0.260 ns
    40.448 ns net_112123 (p.csrs.cdat_i[58])
        lc40_27_27_2 (LogicCell40) in0 [setup]: 0.400 ns
    40.848 ns net_107962 (p.csrs.mbadaddr[58])

Resolvable net names on path:
     0.640 ns ..  7.106 ns p.rst
     7.555 ns ..  8.516 ns $abc$12771$n1739
     8.965 ns ..  9.926 ns $abc$12771$n1780_1
    10.241 ns .. 11.371 ns $abc$12771$n1779
    11.819 ns .. 13.152 ns $abc$12771$n1778_1
    13.552 ns .. 17.585 ns $abc$12771$n1777
    18.033 ns .. 18.994 ns p.alu.b[1]
    19.254 ns .. 19.254 ns $auto$alumacc.cc:470:replace_alu$1417.C[2]
    19.380 ns .. 19.380 ns $auto$alumacc.cc:470:replace_alu$1417.C[3]
    19.506 ns .. 19.506 ns $auto$alumacc.cc:470:replace_alu$1417.C[4]
    19.632 ns .. 19.632 ns $auto$alumacc.cc:470:replace_alu$1417.C[5]
    19.759 ns .. 19.759 ns $auto$alumacc.cc:470:replace_alu$1417.C[6]
    19.885 ns .. 20.081 ns $auto$alumacc.cc:470:replace_alu$1417.C[7]
    20.208 ns .. 20.208 ns $auto$alumacc.cc:470:replace_alu$1417.C[8]
    20.334 ns .. 20.334 ns $auto$alumacc.cc:470:replace_alu$1417.C[9]
    20.460 ns .. 20.460 ns $auto$alumacc.cc:470:replace_alu$1417.C[10]
    20.586 ns .. 20.586 ns $auto$alumacc.cc:470:replace_alu$1417.C[11]
    20.713 ns .. 20.713 ns $auto$alumacc.cc:470:replace_alu$1417.C[12]
    20.839 ns .. 20.839 ns $auto$alumacc.cc:470:replace_alu$1417.C[13]
    20.965 ns .. 20.965 ns $auto$alumacc.cc:470:replace_alu$1417.C[14]
    21.091 ns .. 21.288 ns $auto$alumacc.cc:470:replace_alu$1417.C[15]
    21.414 ns .. 21.414 ns $auto$alumacc.cc:470:replace_alu$1417.C[16]
    21.540 ns .. 21.540 ns $auto$alumacc.cc:470:replace_alu$1417.C[17]
    21.666 ns .. 21.666 ns $auto$alumacc.cc:470:replace_alu$1417.C[18]
    21.793 ns .. 21.793 ns $auto$alumacc.cc:470:replace_alu$1417.C[19]
    21.919 ns .. 21.919 ns $auto$alumacc.cc:470:replace_alu$1417.C[20]
    22.045 ns .. 22.045 ns $auto$alumacc.cc:470:replace_alu$1417.C[21]
    22.171 ns .. 22.171 ns $auto$alumacc.cc:470:replace_alu$1417.C[22]
    22.298 ns .. 22.494 ns $auto$alumacc.cc:470:replace_alu$1417.C[23]
    22.620 ns .. 22.620 ns $auto$alumacc.cc:470:replace_alu$1417.C[24]
    22.746 ns .. 22.746 ns $auto$alumacc.cc:470:replace_alu$1417.C[25]
    22.873 ns .. 22.873 ns $auto$alumacc.cc:470:replace_alu$1417.C[26]
    22.999 ns .. 22.999 ns $auto$alumacc.cc:470:replace_alu$1417.C[27]
    23.125 ns .. 23.125 ns $auto$alumacc.cc:470:replace_alu$1417.C[28]
    23.251 ns .. 23.251 ns $auto$alumacc.cc:470:replace_alu$1417.C[29]
    23.378 ns .. 23.378 ns $auto$alumacc.cc:470:replace_alu$1417.C[30]
    23.504 ns .. 23.700 ns $auto$alumacc.cc:470:replace_alu$1417.C[31]
    23.826 ns .. 23.826 ns $auto$alumacc.cc:470:replace_alu$1417.C[32]
    23.953 ns .. 23.953 ns $auto$alumacc.cc:470:replace_alu$1417.C[33]
    24.079 ns .. 24.079 ns $auto$alumacc.cc:470:replace_alu$1417.C[34]
    24.205 ns .. 24.205 ns $auto$alumacc.cc:470:replace_alu$1417.C[35]
    24.331 ns .. 24.331 ns $auto$alumacc.cc:470:replace_alu$1417.C[36]
    24.458 ns .. 24.458 ns $auto$alumacc.cc:470:replace_alu$1417.C[37]
    24.584 ns .. 24.584 ns $auto$alumacc.cc:470:replace_alu$1417.C[38]
    24.710 ns .. 24.907 ns $auto$alumacc.cc:470:replace_alu$1417.C[39]
    25.033 ns .. 25.033 ns $auto$alumacc.cc:470:replace_alu$1417.C[40]
    25.159 ns .. 25.159 ns $auto$alumacc.cc:470:replace_alu$1417.C[41]
    25.285 ns .. 25.285 ns $auto$alumacc.cc:470:replace_alu$1417.C[42]
    25.411 ns .. 25.411 ns $auto$alumacc.cc:470:replace_alu$1417.C[43]
    25.538 ns .. 25.538 ns $auto$alumacc.cc:470:replace_alu$1417.C[44]
    25.664 ns .. 25.664 ns $auto$alumacc.cc:470:replace_alu$1417.C[45]
    25.790 ns .. 25.790 ns $auto$alumacc.cc:470:replace_alu$1417.C[46]
    25.916 ns .. 26.113 ns $auto$alumacc.cc:470:replace_alu$1417.C[47]
    26.239 ns .. 26.239 ns $auto$alumacc.cc:470:replace_alu$1417.C[48]
    26.365 ns .. 26.365 ns $auto$alumacc.cc:470:replace_alu$1417.C[49]
    26.492 ns .. 26.492 ns $auto$alumacc.cc:470:replace_alu$1417.C[50]
    26.618 ns .. 26.618 ns $auto$alumacc.cc:470:replace_alu$1417.C[51]
    26.744 ns .. 26.744 ns $auto$alumacc.cc:470:replace_alu$1417.C[52]
    26.870 ns .. 26.870 ns $auto$alumacc.cc:470:replace_alu$1417.C[53]
    26.997 ns .. 26.997 ns $auto$alumacc.cc:470:replace_alu$1417.C[54]
    27.123 ns .. 27.319 ns $auto$alumacc.cc:470:replace_alu$1417.C[55]
    27.445 ns .. 27.445 ns $auto$alumacc.cc:470:replace_alu$1417.C[56]
    27.572 ns .. 27.572 ns $auto$alumacc.cc:470:replace_alu$1417.C[57]
    27.698 ns .. 27.957 ns $auto$alumacc.cc:470:replace_alu$1417.C[58]
    28.273 ns .. 29.234 ns p.alu.sumL[58]
    29.549 ns .. 30.139 ns $abc$12771$n2684
    30.454 ns .. 31.043 ns $abc$12771$n2683
    31.359 ns .. 34.220 ns $abc$12771$n2682
    34.669 ns .. 36.002 ns $abc$12771$n3143
    36.402 ns .. 39.410 ns $abc$12771$n4843
    39.859 ns .. 40.448 ns p.csrs.cdat_i[58]
                  lcout -> p.csrs.mbadaddr[58]

Total number of logic levels: 71
Total path delay: 40.85 ns (24.48 MHz)

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