Verilator open-source SystemVerilog simulator and lint system
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Updated
Jun 10, 2024 - C++
Verilator open-source SystemVerilog simulator and lint system
Sol-1: A CPU/Computer System made from 74 series logic.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Opensource DDR3 Controller
Veryl: A Modern Hardware Description Language
BDD Gherkin implementation in native SystemVerilog, based on UVM.
A (mostly) EDTASM+ compatible MC6809 Assembler using yacc/bison
High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in EECS 112L course on Organization of Computers.
SystemVerilog to Verilog conversion
Designing Single-Cycle Microprocessor without Interlocked Pipeline Stages (MIPS) using Verilog.
SystemVerilog compiler and language services
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
My technical notes as bite-sized executable programs
HDL support for VS Code
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