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rtl

Here are 1,039 public repositories matching this topic...

verilator

verilator / verilator

Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Jun 10, 2024
C++

hdl-registers

hdl-registers / hdl-registers

An open-source HDL register code generator fast enough to run in real time.

python c html asic generator fpga cplusplus register vhdl eda rtl csr axi axi-lite register-interface

Updated Jun 10, 2024
Python

veryl

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog

Updated Jun 10, 2024
Rust

sean-galloway / RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

rtl system-verilog uvm-verification

Updated Jun 10, 2024
SystemVerilog

williaml33moore / bathtub

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Jun 10, 2024
SystemVerilog

chili-chips-ba / openeye-CamSI

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.

opensource video fpga camera serdes ddr raspberrypi rtl isp vlc hdmi systemverilog csi hd image-sensor uhd low-budget imx283 signal-integrity

Updated Jun 10, 2024
Verilog

scrabble-solver

kamilmielnik / scrabble-solver

Free, open-source, and cross-platform analysis tool for Scrabble, Super Scrabble & Literaki. Quickly find top scoring words using given letters and board state. Available in English, French, German, Persian, Polish, Romanian & Spanish.

react redux nodejs crossword analysis nextjs solver rtl next scrabble scrabble-dictionary scrabble-solver scrabble-game quackle scrabble-word-finder literaki super-scrabble literaxx

Updated Jun 9, 2024
TypeScript

chili-chips-ba / openCologne

Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples.

design embedded fpga hls digital pcb rtl systemverilog soc risc-v gatemate colognechip

Updated Jun 9, 2024
C++

The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

cpp tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Jun 10, 2024
Verilog

postcss-rtlcss

elchininet / postcss-rtlcss

PostCSS plugin to automatically build Cascading Style Sheets (CSS) with Left-To-Right (LTR) and Right-To-Left (RTL) rules using RTLCSS

css plugin postcss ltr rtl postcss-plugin rtlcss arabic hebrew right-to-left left-to-right rtl-adaptivity direction postcss-rtlcss rtl-plugin automatic-rtl automatic-ltr

Updated Jun 9, 2024
TypeScript

The-OpenROAD-Project / OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

tcl eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

Updated Jun 10, 2024
Verilog

JoyenBenitto / Quark

Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)

rtl risc-v bluespec-systemverilog bsv riscv32

Updated Jun 9, 2024
Bluespec

neorv32

stnolting / neorv32

🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Updated Jun 8, 2024
C

chisel

chipsalliance / chisel

Chisel: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Jun 10, 2024
Scala

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Jun 7, 2024
Scala

rggen / rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Jun 7, 2024
Ruby

rggen / rggen-vhdl

VHDL plugin for RgGen

Updated Jun 7, 2024
Ruby

rggen / rggen-verilog

Verilog writer plugin for RgGen

Updated Jun 7, 2024
Ruby

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Jun 10, 2024
SystemVerilog

rggen / rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

rtl systemverilog uvm ral

Updated Jun 7, 2024
Ruby

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