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Machine learning on FPGAs using HLS
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Updated
Jun 10, 2024
Assembly
A LeNet-5 implementation using C language and FPGA, obtaining more performance (Hardware) together with greater versatility (Software), uniting the two worlds. Hardening the Software and Softening the Hardware, to something in between, like Molten Iron, so a Moltenware implementation.
HAL – The Hardware Analyzer
Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
Updated
Jun 10, 2024
SystemVerilog
Over-engineered SDR development board
Updated
Jun 10, 2024
VHDL
Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples.
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
Updated
Jun 10, 2024
Verilog
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
Updated
Jun 10, 2024
Verilog
This repo contains the work developed in the SIEAV Master practices 🎓✏️📚
Updated
Jun 10, 2024
VHDL
An Open-source FPGA IP Generator
Updated
Jun 10, 2024
Verilog
Squishy hardware design files
Run Time for AIE and FPGA based platforms
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
Updated
Jun 10, 2024
Verilog
Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.
Updated
Jun 10, 2024
Python
A small project I had in uni.
Updated
Jun 10, 2024
VHDL
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Updated
Jun 10, 2024
VHDL
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Updated
Jun 10, 2024
Verilog
A modern hardware definition language and toolchain based on Python
Updated
Jun 10, 2024
Python
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